公开(公告)号：US20250113487A1

公开(公告)日：2025-04-03

申请号：US18978230

申请日：2024-12-12

Applicant: Micron Technology, Inc.

Inventor： Collin Howder ,  M. Jared Barclay ,  Bhavesh Bhartia ,  Chet E. Carter ,  John D. Hopkins ,  Andrew Li ,  Haoyu Li ,  Alyssa N. Scarbrough ,  Grady S. Waldo

IPC: H10B43/27 ,  H10B41/27

Abstract: Integrated circuitry comprising a memory array comprises strings of memory cells comprising laterally-spaced memory blocks individually comprising a first vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple with conductor material of the conductor tier. The conductive tiers individually comprise a horizontally-elongated conductive line. A second vertical stack is aside the first vertical stack. The second vertical stack comprises an upper portion and a lower portion. The upper portion comprises vertically-alternating first insulating tiers and second insulating tiers that are of different insulative compositions relative one another. The lower portion comprises a horizontal line above the conductor tier that runs parallel with the laterally-spaced memory blocks in the first vertical stack. Other embodiments, including method, are disclosed.

公开(公告)号：US12255143B2

公开(公告)日：2025-03-18

申请号：US17187481

申请日：2021-02-26

Applicant: Micron Technology, Inc.

Inventor： Alyssa N. Scarbrough ,  Jordan D. Greenlee ,  John D. Hopkins

IPC: H01L23/532 ,  H01L23/528 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A microelectronic device includes a stack structure, a staircase structure, composite pad structures, and conductive contact structures. The stack structure includes vertically alternating conductive structures and insulative structures arranged in tiers. Each of the tiers individually includes one of the conductive structures and one of the insulative structures. The staircase structure has steps including edges of at least some of the tiers of the stack structure. The composite pad structures are on the steps of the staircase structure. Each of the composite pad structures includes a lower pad structure, and an upper pad structure overlying the lower pad structure and having a different material composition than the lower pad structure. The conductive contact structures extend through the composite pad structures and to the conductive structures of the stack structure. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.

公开(公告)号：US12213311B2

公开(公告)日：2025-01-28

申请号：US17670685

申请日：2022-02-14

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Alyssa N. Scarbrough

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a lower portion of a stack that will comprise vertically-alternating first tiers and second tiers on a substrate. The stack comprises laterally-spaced memory-block regions, Material of the first tiers is of different composition from material of the second tiers. Horizontally-elongated lines are formed in the lower portion that are individually between immediately-laterally-adjacent of the memory-block regions. The lines comprise sacrificial material. The lines individually comprise laterally-opposing projections longitudinally therealong in a lowest of the first tiers. The vertically-alternating first tiers and second tiers of an upper portion of the stack are formed above the lower portion and the lines, and channel-material strings are formed that extend through the first tiers and the second tiers in the upper portion to the lower portion. Horizontally-elongated trenches are formed into the stack that are individually between the immediately-laterally-adjacent memory-block regions and extend to the line there-between. The sacrificial material of the lines and projections is removed through the trenches. Intervening material is formed in the trenches and void-spaces left as a result of the removing of the sacrificial material of the lines. Other embodiments are disclosed.

公开(公告)号：US12176034B2

公开(公告)日：2024-12-24

申请号：US17583472

申请日：2022-01-25

Applicant: Micron Technology, Inc.

Inventor： Alyssa N. Scarbrough ,  M. Jared Barclay ,  John D. Hopkins

IPC: H01L29/76 ,  G11C16/04 ,  H01L23/522 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers directly above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple to conductor material of the conductor tier. A through-array-via (TAV) region comprises TAVs that individually extend through a lowest of the conductive tiers. Insulative rings are in the lowest conductive tier in the TAV region. Individual of the insulative rings encircle individual of the TAVs. The insulative rings extend through the lowest conductive tier and into the conductor tier. Outer rings are in the lowest conductive tier that individually encircle one of the individual insulative rings that encircle the individual TAVs. Other embodiments, including method, are disclosed.

公开(公告)号：US20240251555A1

公开(公告)日：2024-07-25

申请号：US18585372

申请日：2024-02-23

Applicant: Micron Technology, Inc.

Inventor： Alyssa N. Scarbrough ,  John D. Hopkins ,  Jordan D. Greenlee

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/35 ,  H10B43/40

Abstract: Some embodiments include an integrated assembly having a first memory region, a second memory region offset from the first memory region, and an intermediate region between the first and second memory regions. Channel-material-pillars are arranged within the memory regions. Conductive posts are arranged within the intermediate region. A panel extends across the memory regions and the intermediate region. The panel is laterally between a first memory-block-region and a second memory-block-region. Doped-semiconductor-material is within the memory regions and the intermediate region, and is directly adjacent to the panel. The doped-semiconductor-material is at least part of conductive source structures within the memory regions. Insulative rings laterally surround lower regions of the conductive posts and are between the conductive posts and the doped-semiconductor-material. Insulative liners are along upper regions of the conductive posts. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11948639B2

公开(公告)日：2024-04-02

申请号：US17368395

申请日：2021-07-06

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Alyssa N. Scarbrough

IPC: H10B41/27 ,  G11C16/04 ,  H01L21/28 ,  H01L29/423 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: G11C16/0483 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42328 ,  H01L29/42344 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers comprising laterally-spaced memory-block regions having horizontally-elongated trenches there-between. Two of the first tiers have different vertical thicknesses relative one another. Channel-material strings of memory cells extend through the first tiers and the second tiers. Through the horizontally-elongated trenches, first conductive material is formed in void space in the two first tiers. The first conductive material fills the first tier of the two first tiers that has a smaller of the different vertical thicknesses in individual of the memory-block regions. The first conductive material less-than-fills the first tier of the two first tiers that has a larger of the different vertical thicknesses in the individual memory-block regions. Through the horizontally-elongated trenches, the first conductive material is isotropically etched from the first tier having the larger vertical thickness in the individual memory-block regions to leave the first conductive material in the first tier having the smaller vertical thickness in the individual memory-block regions. After the isotropically etching of the first conductive material and through the horizontally-elongated trenches, second conductive material is formed in the first tier having the larger vertical thickness in the individual memory-block regions. Other embodiments, including structure independent of method, are disclosed.

公开(公告)号：US20240081070A1

公开(公告)日：2024-03-07

申请号：US17929965

申请日：2022-09-06

Applicant: Micron Technology, Inc.

Inventor： Alyssa N. Scarbrough ,  John D. Hopkins ,  Jordan D. Greenlee

IPC: H01L27/1157 ,  H01L27/11524 ,  H01L27/11553 ,  H01L27/11582

CPC classification number: H01L27/1157 ,  H01L27/11524 ,  H01L27/11553 ,  H01L27/11582

Abstract: Source terminals of memory devices and related apparatuses, computing systems, and methods are disclosed. An apparatus includes a first polysilicon material, a second polysilicon material offset from the first polysilicon material, an intervening polysilicon material between the first polysilicon material and the second polysilicon material, and pillars defining memory cells. The pillars extend through the second polysilicon material and a proximal portion of the intervening polysilicon material into the first polysilicon material. The one or more insulative materials are at a distal edge of the intervening polysilicon material. The intervening polysilicon material is thicker at the distal edge than at the pillars. A method includes removing, using an isotropic etch process, portions of the first polysilicon material and the second polysilicon material in a trench and forming the intervening polysilicon material between the first polysilicon material and the second polysilicon material.

公开(公告)号：US20240074202A1

公开(公告)日：2024-02-29

申请号：US17897350

申请日：2022-08-29

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Alyssa N. Scarbrough

IPC: H01L27/1157 ,  H01L21/306 ,  H01L21/308 ,  H01L27/11578

CPC classification number: H01L27/1157 ,  H01L21/30608 ,  H01L21/3086 ,  H01L27/11578

Abstract: A method used in forming memory circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers. The stack extends from a memory-array region into a stair-step region. The stair-step region comprises a flight of stairs extending along a first direction. The first tiers are conductive and the second tiers are insulative at least in a finished-circuitry construction. An anisotropically-etched spacer is formed extending along the first direction directly above the flight of stairs. The anisotropically-etched spacer is used as a mask while etching through one of the first tiers and one of the second tiers in individual of the stairs to form multiple different-depth treads in the individual stairs along a second direction that is orthogonal to the first direction. Individual of the treads comprise conducting material of individual of the first tiers in the finished-circuitry construction. Other aspects, including structure independent of method, are disclosed.

公开(公告)号：US20240074182A1

公开(公告)日：2024-02-29

申请号：US17897399

申请日：2022-08-29

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Alyssa N. Scarbrough

IPC: H01L27/11582 ,  H01L23/535 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  H01L23/535 ,  H01L27/11556

Abstract: Memory circuitry comprising strings of memory cells comprises a stack comprising vertically-alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers in a memory-array region. The insulative tiers and the conductive tiers extend from the memory-array region into a stair-step region. The stair-step region comprises a flight of stairs extending along a first direction. Multiple different-depth treads in individual of the stairs extend along a second direction that is orthogonal to the first direction. Individual of the multiple different-depth treads comprise conducting material of one of the conductive tiers. The multiple different-depth treads in the individual stairs comprise in lateral-succession along the second direction a first higher-depth tread, a lower-depth tread, and a second higher-depth tread. Methods are also disclosed.

公开(公告)号：US20240071816A1

公开(公告)日：2024-02-29

申请号：US17896919

申请日：2022-08-26

Applicant: Micron Technology, Inc.

Inventor： Alyssa N. Scarbrough ,  Lifang Xu ,  Jordan D. Greenlee

IPC: H01L21/768 ,  H01L23/535 ,  H01L27/11526 ,  H01L27/11573

CPC classification number: H01L21/76816 ,  H01L21/76805 ,  H01L21/76846 ,  H01L21/76865 ,  H01L21/76895 ,  H01L23/535 ,  H01L27/11526 ,  H01L27/11573

Abstract: Methods, systems, and devices for staircase formation in a memory array are described. A liner composed of a first liner material may be deposited on a tread and a first portion of the liner may be doped. After doping the first portion of the liner, a second portion of the liner may be converted into a second liner material using a chemical process. After converting the second portion of the liner into the second liner material, the first portion of the liner material may be removed so that a subsequent removal process can expose a first sub-tread. After exposing the first sub-tread, the second portion of the liner may be removed so that a second sub-tread is exposed.