公开(公告)号：US20130024736A1

公开(公告)日：2013-01-24

申请号：US13633158

申请日：2012-10-02

Applicant: MICRON TECHNOLOGY, INC

Inventor： Frankie F. Roohparvar ,  Vishal Sarin ,  Jung S. Hoei

IPC: H03M13/05 ,  G06F11/00 ,  G11C29/08

CPC classification number: G06F11/1076 ,  G06F11/1072 ,  G11C29/12005

Abstract: Memory devices that, in a particular embodiment, receive and transmit analog data signals representative of bit patterns of two or more bits such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming error correction code (ECC) and metadata into such memory devices includes storing the ECC and metadata at different bit levels per cell based on an actual error rate of the cells. The ECC and metadata can be stored with the data block at a different bit level than the data block. If the area of memory in which the block of data is stored does not support the desired reliability for the ECC and metadata at a particular bit level, the ECC and metadata can be stored in other areas of the memory array at different bit levels.

Abstract translation: 在特定实施例中，存储设备接收和发送表示两个或多个位的位模式的模拟数据信号，以便于相对于传送指示各个位的数据信号的设备的数据传输速率的增加。 编程错误校正码（ECC）和元数据到这种存储器设备中包括基于单元的实际错误率将ECC和元数据存储在每个小区的不同比特级。 ECC和元数据可以与数据块存储在与数据块不同的位级别。 如果其中存储数据块的存储器区域不支持在特定位级别的ECC和元数据的期望的可靠性，则ECC和元数据可以以不同的位电平存储在存储器阵列的其他区域中。

公开(公告)号：US20220115071A1

公开(公告)日：2022-04-14

申请号：US17555728

申请日：2021-12-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Vishal Sarin ,  Allahyar Vahidimowlavi

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/34 ,  G11C11/56

Abstract: Memory having an array of memory cells might include control logic configured to cause the memory to program each memory cell of a plurality of memory cells whose respective data state is higher than or equal to a first particular data state of a plurality of data states while inhibiting programming of each memory cell of the plurality of memory cells whose respective data state is lower than the first particular data state, and program each memory cell of the plurality of memory cells whose respective data state is lower than or equal to a second particular data state of the plurality of data states after programming each memory cell of the plurality of memory cells whose respective data state is higher than or equal to the first particular data state.

公开(公告)号：US10770145B2

公开(公告)日：2020-09-08

申请号：US16298313

申请日：2019-03-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Vishal Sarin ,  Allahyar Vahidimowlavi

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/34 ,  G11C11/56

Abstract: Method of operating a memory include increasing respective threshold voltages of a first subset of memory cells of a plurality of memory cells to threshold voltage levels higher than a particular voltage level in response to applying a first plurality of programming pulses, and subsequently increasing respective threshold voltages of a second subset of memory cells of the plurality of memory cells to threshold voltage levels lower than the particular voltage level in response to applying a second plurality of programming pulses, wherein the first plurality of programming pulses have respective voltage levels within a first range of voltage levels, the second plurality of programming pulses have respective voltage levels within a second range of voltage levels, and a lowest voltage level of the first range of voltage levels is lower than or equal to a highest voltage level of the second range of voltage levels.

公开(公告)号：US20180096722A1

公开(公告)日：2018-04-05

申请号：US15831718

申请日：2017-12-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Vishal Sarin ,  Allahyar Vahidimowlavi

IPC: G11C11/56 ,  G11C16/34 ,  G11C16/10 ,  G11C16/04

CPC classification number: G11C11/5628 ,  G11C16/0408 ,  G11C16/0458 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3427 ,  G11C2211/562 ,  G11C2211/5622 ,  G11C2211/5642 ,  G11C2211/5648

Abstract: Memory devices include control logic configured to set a first start program voltage and a first stop program voltage, to load actual first data for cells to be programmed to a level greater than or equal to a first level, and to load inhibit data for cells to be programmed to a level less than a second level. After programming the cells to be programmed to the level greater than or equal to the first level, the control logic is further configured to set a second start program voltage and a second stop program voltage, to load inhibit data for the cells programmed to the level greater than or equal to the first level, and to load actual second data for the cells to be programmed to the level less than the second level, wherein the first level is one level higher than the second level.

公开(公告)号：US09502101B2

公开(公告)日：2016-11-22

申请号：US14725749

申请日：2015-05-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Vishal Sarin ,  Allahyar Vahidimowlavi

IPC: G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34

CPC classification number: G11C11/5628 ,  G11C16/0408 ,  G11C16/0458 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3427 ,  G11C2211/562 ,  G11C2211/5622 ,  G11C2211/5642 ,  G11C2211/5648

Abstract: A first memory cell is programmed to a first level using a first set of program pulses within a first programming voltage range. A second memory cell to be programmed to a second level less than the first level is inhibited while programming the first memory cell to the first level. After programming the first memory cell to the first level, the second memory cell is programmed to the second level using a second set of program pulses within a second programming voltage range, where the first programming voltage range overlaps the second programming voltage range. The first memory cell that is programmed to the first level is inhibited while programming the second memory cell to the second level.

Abstract translation: 使用第一编程电压范围内的第一组编程脉冲将第一存储单元编程为第一电平。 在将第一存储器单元编程到第一电平时，禁止要编程到小于第一电平的第二电平的第二存储器单元。 在将第一存储器单元编程到第一电平之后，使用第二编程电压范围内的第二组编程脉冲将第二存储单元编程为第二电平，其中第一编程电压范围与第二编程电压范围重叠。 在将第二存储器单元编程到第二级时，禁止编程到第一级的第一存储单元。

公开(公告)号：US09025388B2

公开(公告)日：2015-05-05

申请号：US14045492

申请日：2013-10-03

Applicant: Micron Technology, Inc.

Inventor： Violante Moschiano ,  Frankie Roohparvar ,  Giovanni Santin ,  Vishal Sarin ,  Allahyar Vahidimowlavi ,  Tommaso Vali

IPC: G11C16/04 ,  G11C16/10 ,  G11C11/56 ,  G11C16/34 ,  G11C11/404

CPC classification number: G11C16/10 ,  G11C11/404 ,  G11C11/5628 ,  G11C16/3404

Abstract: This disclosure concerns memory kink compensation. One method embodiment includes applying a number of sequentially incrementing programming pulses to a memory cell, with the sequential programming pulses incrementing by a first programming pulse step voltage magnitude. A seeding voltage is applied after applying the number of sequentially incrementing programming pulses. A next programming pulse is applied after applying the seeding voltage, with the next programming pulse being adjusted relative to a preceding one of the sequentially incrementing programming pulses by a second programming pulse step voltage magnitude. The second programming pulse step voltage magnitude can be less than the first programming pulse step voltage magnitude.

Abstract translation: 本公开涉及存储器扭结补偿。 一个方法实施例包括将多个顺序递增的编程脉冲施加到存储器单元，其中顺序编程脉冲通过第一编程脉冲阶跃电压幅度递增。 在施加顺序递增的编程脉冲数之后施加接种电压。 在施加播种电压之后施加下一个编程脉冲，其中下一个编程脉冲相对于先前的一个顺序递增的编程脉冲通过第二编程脉冲阶跃电压幅度被调整。 第二个编程脉冲阶跃电压幅度可以小于第一个编程脉冲阶跃电压幅度。

公开(公告)号：US08995182B2

公开(公告)日：2015-03-31

申请号：US13796602

申请日：2013-03-12

Applicant: Micron Technology, Inc.

Inventor： Frankie F. Roohparvar ,  Vishal Sarin ,  Jung-Sheng Hoei

IPC: G11C16/10 ,  G11C11/56 ,  G11C16/34

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/3418

Abstract: Memory devices adapted to receive and transmit analog data signals representative of bit patterns of two or more bits facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming of such memory devices includes initially programming a cell with a coarse programming pulse to move its threshold voltage in a large step close to the programmed state. The neighboring cells are then programmed using coarse programming. The algorithm then returns to the initially programmed cells that are then programmed with one or more fine pulses that slowly move the threshold voltage in smaller steps to the final programmed state threshold voltage.

Abstract translation: 适于接收和发送表示两个或多个位的位模式的模拟数据信号的存储器件有助于相对于传送指示各个位的数据信号的器件的数据传输速率的增加。 这种存储器件的编程包括：用粗略的编程脉冲对单元进行初始编程，使其阈值电压以接近编程状态的大步进移动。 然后使用粗略编程对相邻单元进行编程。 然后，该算法返回到初始编程的单元，然后使用一个或多个精细脉冲编程，该精细脉冲以较小步长将阈值电压缓慢移动到最终编程状态阈值电压。

公开(公告)号：US08953374B2

公开(公告)日：2015-02-10

申请号：US14107038

申请日：2013-12-16

Applicant: Micron Technology, Inc.

Inventor： Frankie F. Roohparvar ,  Vishal Sarin ,  Jung-Sheng Hoei

IPC: G11C16/04 ,  G11C16/10 ,  G11C11/56

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C2211/5641

Abstract: Methods and solid state drives are disclosed, for example a solid state drive that is adapted to receive and transmit analog data signals representative of bit patterns of three or more levels (such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits). Programming of the solid state drive, comprising an array of non-volatile memory cells, might include adjusting the level of each memory cell being programmed in response to a desired performance level of a controller circuit.

公开(公告)号：US20140298088A1

公开(公告)日：2014-10-02

申请号：US14308040

申请日：2014-06-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： William H. Radke ,  Vishal Sarin ,  Jung-Sheng Hoei

IPC: G06F11/10 ,  G11C29/52

CPC classification number: G06F11/1072 ,  G06F12/0246 ,  G06F2212/7205 ,  G06F2212/7208 ,  G11C11/5628 ,  G11C29/52 ,  G11C2211/5641

Abstract: Methods for managing data stored in a memory device facilitate managing utilization of memory of different densities. The methods include reading first data from a first number of pages or blocks of memory cells having a first density, performing a data handling operation on the read first data to generate second data, and writing the second data to a second number of pages or blocks of memory cells having a second density, wherein the second density is different than the first density, and wherein the second number is different than the first number.

Abstract translation: 用于管理存储在存储设备中的数据的方法便于管理不同密度的存储器的利用。 所述方法包括从具有第一密度的第一页数或块的存储单元读取第一数据，对读取的第一数据执行数据处理操作以产生第二数据，以及将第二数据写入第二数量的页或块 的具有第二密度的存储单元，其中所述第二密度不同于所述第一密度，并且其中所述第二数量不同于所述第一密度。

公开(公告)号：US08737127B2

公开(公告)日：2014-05-27

申请号：US13770059

申请日：2013-02-19

Applicant: Micron Technology, Inc.

Inventor： Vishal Sarin ,  Jung-Sheng Hoei ,  Jonathan Pabustan ,  Frankie F. Roohparvar

IPC: G11C16/04

CPC classification number: G11C11/5642 ,  G11C7/16 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C27/005 ,  G11C2211/5621 ,  G11C2211/5622 ,  G11C2211/5642 ,  G11C2216/14

Abstract: A memory controller has a digital signal processor. The digital signal processor is configured to output a digital data signal of M+N bits of program data intended for programming a memory cell of a memory device. The digital signal processor is configured to receive a digital data signal of M+L bits read from the memory cell of the memory device and to retrieve from the received digital data signal M bits of data that were stored in the memory cell.

Abstract translation: 存储器控制器具有数字信号处理器。 数字信号处理器被配置为输出用于对存储器件的存储器单元进行编程的程序数据的M + N位的数字数据信号。 数字信号处理器被配置为接收从存储器件的存储器单元读取的M + L位的数字数据信号，并从接收的数字数据信号M中取回存储在存储单元中的数据位。