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公开(公告)号：US20170148493A1
公开(公告)日：2017-05-25
申请号：US15212340
申请日：2016-07-18
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yu-Ming Chang , Hsiang-Pang Li , Hsin-Yu Chang , Chien-Chung Ho , Yuan-Hao Chang
IPC: G11C7/00
Abstract: An erasing method and a memory device are provided. The memory device includes a plurality of memory blocks. Each of the memory blocks has n sub-blocks. The erasing method includes the following steps. A first erase region is selected from a first memory block of the memory blocks, and the first erase region includes at least one sub-block. A sub-block erase operation is performed on the first erase region of the first memory block.
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公开(公告)号：US09628114B2
公开(公告)日：2017-04-18
申请号：US14794059
申请日：2015-07-08
Applicant: Macronix International Co., Ltd.
Inventor： Yu-Ming Huang , Hsiang-Pang Li , Hsie-Chia Chang
CPC classification number: H03M13/616 , H03M13/13 , H03M13/618 , H03M13/635 , H04L1/0057 , H04L1/0067
Abstract: A method for increasing coding reliability includes generating a generator matrix for an extended polar code including a standard polar code part and an additional frozen part. The standard polar code part has N bit-channels, including K information bit-channels and N−K frozen bit-channels. The additional frozen part has q additional frozen bit-channels. Among the K information bit-channels, q information bit-channels are re-polarized using the q additional frozen bit-channels. The method further includes receiving an input vector including K information bits and N+q−K frozen bits, and transforming, using the generator matrix, the input vector to an output vector including N+q encoded bits. The K information bits are allocated to the K information bit-channels, and the N+q−K frozen bits are allocated to the N−K frozen bit-channels and the q additional frozen bit-channels.
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公开(公告)号：US09558108B2
公开(公告)日：2017-01-31
申请号：US14018149
申请日：2013-09-04
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yu-Ming Chang , Yung-Chun Li , Hsing-Chen Lu , Hsiang-Pang Li , Cheng-Yuan Wang , Yuan-Hao Chang , Tei-Wei Kuo
CPC classification number: G06F12/0246 , G06F2212/7205 , G11C16/0483 , G11C16/16 , G11C16/3427
Abstract: A method for managing block erase operations is provided for an array of memory cells including erasable blocks of memory cells in the array. The method comprises maintaining status data for a plurality of sub-blocks of the erasable blocks of the array. The status data indicate whether the sub-blocks are currently accessible and whether the sub-blocks are invalid. The method comprises, in response to a request to erase a selected sub-block of a particular erasable block, issuing an erase command to erase the particular block if the other sub-blocks of the particular erasable block are invalid, else updating the status data to indicate that the selected sub-block is invalid.
Abstract translation: 提供了一种用于管理块擦除操作的方法，用于包括阵列中的可擦除存储单元块的存储单元阵列。 该方法包括维护阵列的可擦除块的多个子块的状态数据。 状态数据指示子块当前是否可访问以及子块是否无效。 该方法响应于擦除特定可擦除块的所选子块的请求，如果特定可擦除块的其他子块无效则发出擦除命令以擦除特定块，否则更新状态数据 以指示所选择的子块是无效的。
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公开(公告)号：US20160300617A1
公开(公告)日：2016-10-13
申请号：US14684561
申请日：2015-04-13
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yu-Ming Chang , Hsiang-Pang Li , Hung-Sheng Chang , Chih-Chang Hsieh , Kuo-Pin Chang
IPC: G11C16/16
Abstract: A memory device and an erase method for the memory device are provided. The memory device includes plural blocks and a controller. The plural blocks include at least one first block and at least one second block. The erase method is controlled by the controller and includes the following steps. A first stage erase operation and a second stage erase operation are sequentially performed on the at least one first block in a first time interval and a second time interval. The first stage erase operation and the second stage erase operation are sequentially performed on the at least one second block in the second time interval and a third time interval.
Abstract translation: 提供了一种用于存储器件的存储器件和擦除方法。 存储装置包括多个块和控制器。 多个块包括至少一个第一块和至少一个第二块。 擦除方法由控制器控制，包括以下步骤。 在第一时间间隔和第二时间间隔中对至少一个第一块依次执行第一阶段擦除操作和第二阶段擦除操作。 在第二时间间隔和第三时间间隔中，对至少一个第二块依次执行第一级擦除操作和第二级擦除操作。
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公开(公告)号：US09466384B1
公开(公告)日：2016-10-11
申请号：US14684561
申请日：2015-04-13
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yu-Ming Chang , Hsiang-Pang Li , Hung-Sheng Chang , Chih-Chang Hsieh , Kuo-Pin Chang
Abstract: A memory device and an erase method for the memory device are provided. The memory device includes plural blocks and a controller. The plural blocks include at least one first block and at least one second block. The erase method is controlled by the controller and includes the following steps. A first stage erase operation and a second stage erase operation are sequentially performed on the at least one first block in a first time interval and a second time interval. The first stage erase operation and the second stage erase operation are sequentially performed on the at least one second block in the second time interval and a third time interval.
Abstract translation: 提供了一种用于存储器件的存储器件和擦除方法。 存储装置包括多个块和控制器。 多个块包括至少一个第一块和至少一个第二块。 擦除方法由控制器控制，包括以下步骤。 在第一时间间隔和第二时间间隔中对至少一个第一块依次执行第一阶段擦除操作和第二阶段擦除操作。 在第二时间间隔和第三时间间隔中，对至少一个第二块依次执行第一级擦除操作和第二级擦除操作。
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Patent Agency Ranking
公开(公告)号：US09348748B2
公开(公告)日：2016-05-24
申请号：US14578820
申请日：2014-12-22
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yu-Ming Chang , Hsiang-Pang Li , Hang-Ting Lue , Yuan-Hao Chang , Tei-Wei Kuo
CPC classification number: G06F12/0246 , G06F12/00 , G06F2212/1036 , G06F2212/7211 , G11C16/3495 , G11C29/4401
Abstract: Technology is described that increases endurance of memory devices through heal leveling. Heal leveling is a lightweight solution to distribute healing cycles among memory blocks. Approaches described herein can accomplish heal leveling without introducing a large amount of overhead. Heal leveling significantly improves the access performance and the effective lifetime of memory blocks. By more evenly distributing the heal count it may not be necessary to directly apply wear leveling based on access counts of each block because each block will be more evenly accessed in the long run. Heal leveling may be performed by moving data that is seldom or never modified after creation, such as read-only files, to blocks having suffered the greatest number, or a high number, of healing cycles.
Abstract translation: 技术被描述为通过愈合平整来增加记忆装置的耐久性。 治疗矫正是一种轻量级的解决方案，可以在内存块之间分配愈合周期。 本文描述的方法可以在不引入大量开销的情况下完成愈合平整。 愈合程度显着提高了存储块的访问性能和有效寿命。 通过更均匀地分配治疗计数，可能不需要基于每个块的访问计数来直接应用磨损均衡，因为长期来看每个块将被更均匀地访问。 可以通过将创建后很少或从不修改的数据（例如只读文件）移动到遭受最大数量的块或大量愈合周期来执行愈合调平。
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公开(公告)号：US09336878B2
公开(公告)日：2016-05-10
申请号：US14566453
申请日：2014-12-10
Applicant: Macronix International Co., Ltd.
Inventor： Win San Khwa , Chao-I Wu , Tzu-Hsiang Su , Hsiang-Pang Li
CPC classification number: G11C13/0097 , G11C11/5614 , G11C11/5678 , G11C13/0004 , G11C13/0021 , G11C13/0033 , G11C13/0069 , G11C29/50008 , G11C2213/79 , G11C2213/82
Abstract: A first memory cell including a phase change material. The first memory cell is programmable to store one data value of a plurality of data values. The plurality of data values are represented by a plurality of non-overlapping ranges of resistance of the first memory cell. At least one testing pulse is applied to the first memory cell to establish a cell resistance of the first memory cell in an intermediate range of resistance, the intermediate range of resistance in between first and second adjacent ranges in the plurality of non-overlapping ranges of resistance representing the plurality of data values. After applying the at least one testing pulse to the first memory cell, it is determined whether to apply at least one healing pulse to repair the first memory cell, depending on relative values of (i) the cell resistance in the intermediate range of resistance and (ii) a reference resistance in the intermediate range of resistance.
Abstract translation: 包括相变材料的第一存储单元。 第一存储器单元可编程以存储多个数据值的一个数据值。 多个数据值由第一存储单元的多个非重叠的电阻范围表示。 至少一个测试脉冲被施加到第一存储器单元，以在电阻的中间范围内建立第一存储器单元的单元电阻，在多个非重叠范围内的第一和第二相邻范围内的电阻的中间范围 表示多个数据值的电阻。 在将至少一个测试脉冲施加到第一存储器单元之后，根据（i）电阻中间范围内的电池电阻的相对值，确定是否施加至少一个愈合脉冲来修复第一存储器单元，以及 （ii）中间电阻范围内的参考电阻。
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公开(公告)号：US09305638B1
公开(公告)日：2016-04-05
申请号：US14526560
申请日：2014-10-29
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yu-Ming Chang , Yung-Chun Li , Chih-Chang Hsieh , Shih-Fu Huang , Hsiang-Pang Li , Yuan-Hao Chang , Tei-Wei Kuo
CPC classification number: G11C11/5628 , G11C7/1006 , G11C11/5642 , G11C16/3427 , G11C16/3459 , G11C2211/5621 , G11C2211/5648
Abstract: Operation methods for a memory device is provided. An operation method for the memory device comprises programming the memory device as described in follows. Data are provided. The data comprise a plurality of codes. Each number of the codes is counted. Then, a mapping rule is generated according to each number of the codes. In the mapping rule, each of the codes is mapped to one of a plurality of verifying voltage levels which are sequentially arranged from low to high. After that, the data are programmed into the memory device according to the mapping rule.
Abstract translation: 提供了存储器件的操作方法。 存储器件的操作方法包括如下所述对存储器件进行编程。 提供数据。 数据包括多个代码。 每个代码数都被计数。 然后，根据代码的数量生成映射规则。 在映射规则中，每个代码被映射到从低到高顺序排列的多个验证电压电平之一。 之后，根据映射规则将数据编程到存储设备中。
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公开(公告)号：US20150371704A1
公开(公告)日：2015-12-24
申请号：US14566453
申请日：2014-12-10
Applicant: Macronix International Co., Ltd.
Inventor： Win San Khwa , Chao-I Wu , Tzu-Hsiang Su , Hsiang-Pang Li
IPC: G11C13/00
CPC classification number: G11C13/0097 , G11C11/5614 , G11C11/5678 , G11C13/0004 , G11C13/0021 , G11C13/0033 , G11C13/0069 , G11C29/50008 , G11C2213/79 , G11C2213/82
Abstract: A first memory cell including a phase change material. The first memory cell is programmable to store one data value of a plurality of data values. The plurality of data values are represented by a plurality of non-overlapping ranges of resistance of the first memory cell. At least one testing pulse is applied to the first memory cell to establish a cell resistance of the first memory cell in an intermediate range of resistance, the intermediate range of resistance in between first and second adjacent ranges in the plurality of non-overlapping ranges of resistance representing the plurality of data values. After applying the at least one testing pulse to the first memory cell, it is determined whether to apply at least one healing pulse to repair the first memory cell, depending on relative values of (i) the cell resistance in the intermediate range of resistance and (ii) a reference resistance in the intermediate range of resistance.
Abstract translation: 包括相变材料的第一存储单元。 第一存储器单元可编程以存储多个数据值的一个数据值。 多个数据值由第一存储单元的多个非重叠的电阻范围表示。 至少一个测试脉冲被施加到第一存储器单元，以在电阻的中间范围内建立第一存储器单元的单元电阻，在多个非重叠范围内的第一和第二相邻范围内的电阻的中间范围 表示多个数据值的电阻。 在将至少一个测试脉冲施加到第一存储器单元之后，根据（i）电阻中间范围内的电池电阻的相对值，确定是否施加至少一个愈合脉冲来修复第一存储器单元，以及 （ii）中间电阻范围内的参考电阻。
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60.发明申请MEMORY SENSING METHOD USING ONE-TIME SENSING TABLE AND ASSOCIATED MEMORY DEVICE 有权使用一次感测表和相关存储器件的存储器感测方法公开(公告)号：US20150332737A1
公开(公告)日：2015-11-19
申请号：US14277087
申请日：2014-05-14
Applicant: Macronix International Co., Ltd.
Inventor： Kin-Chu Ho , Hsiang-Pang Li
CPC classification number: G11C11/56 , G11C7/00 , G11C11/1673 , G11C11/5642 , G11C13/004 , G11C2013/0057
Abstract: A memory sensing method is provided. The memory sensing method comprises the following steps: sensing a first memory unit to obtain a first sensing result; sensing a second memory unit to obtain a second sensing result; and looking up a one-time sensing table according to the first and second sensing results to obtain an output data.
Abstract translation: 提供了一种记忆感测方法。 存储器感测方法包括以下步骤：感测第一存储器单元以获得第一感测结果; 感测第二存储器单元以获得第二感测结果; 并根据第一和第二感测结果查找一次感测表以获得输出数据。
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