公开(公告)号：US20070122962A1

公开(公告)日：2007-05-31

申请号：US11620447

申请日：2007-01-05

申请人： James Chambers ,  Mark Visokay ,  Luigi Colombo

发明人： James Chambers ,  Mark Visokay ,  Luigi Colombo

IPC分类号： H01L21/8238

CPC分类号： H01L21/823857 ,  H01L21/823842 ,  Y10S438/981

摘要： The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively form high-k dielectric layers within NMOS regions. An I/O dielectric layer is formed in core and I/O regions of a semiconductor device (506). The I/O dielectric layer is removed (508) from the core region of the device. A core dielectric layer is formed in the core region (510). A barrier layer is deposited and patterned to expose the NMOS devices of the core region (512). The core dielectric layer is removed from the core NMOS devices (514). A high-k dielectric layer is formed (514) over the core and I/O regions. Then, the high-k dielectric layer is removed (512) from PMOS regions/devices of the core region and the NMOS and PMOS regions/devices of the I/O region.

摘要翻译： 本发明通过提供在NMOS区内选择性地形成高k电介质层的制造方法来促进半导体制造。 在半导体器件（506）的芯和I / O区域中形成I / O电介质层。 从器件的芯区域去除（508）I / O电介质层。 在芯区域（510）中形成芯介质层。 屏蔽层被沉积并图案化以暴露核心区域（512）的NMOS器件。 从核心NMOS器件（514）去除芯介质层。 在核心和I / O区域上形成高k电介质层（514）。 然后，从核心区域的PMOS区域/器件和I / O区域的NMOS和PMOS区域/器件去除高k电介质层（512）。

公开(公告)号：US20070037343A1

公开(公告)日：2007-02-15

申请号：US11200741

申请日：2005-08-10

申请人： Luigi Colombo ,  James Chambers ,  Mark Visokay

发明人： Luigi Colombo ,  James Chambers ,  Mark Visokay

IPC分类号： H01L21/8238

CPC分类号： H01L21/823842 ,  H01L29/66545

摘要： The present invention provides a method of forming a dual work function metal gate microelectronics device 200. In one aspect, the method includes forming nMOS and pMOS stacked gate structures 315a and 315b. The nMOS and pMOS stacked gate structures 315a and 315b each comprise a gate dielectric 205, a first metal layer, 305 located over the gate dielectric 205 and a sacrificial gate layer 310 located over the first metal layer 305. The method further includes removing the sacrificial gate layer 310 in at least one of the nMOS or pMOS stacked gate structures, thereby forming a gate opening 825 and modifying the first metal layer 305 within the gate opening 825 to form a gate electrode with a desired work function.

公开(公告)号：US20050136589A1

公开(公告)日：2005-06-23

申请号：US10738958

申请日：2003-12-17

申请人： Antonio Rotondaro ,  Douglas Mercer ,  Luigi Colombo ,  Mark Visokay ,  Haowen Bu ,  Malcolm Bevan

发明人： Antonio Rotondaro ,  Douglas Mercer ,  Luigi Colombo ,  Mark Visokay ,  Haowen Bu ,  Malcolm Bevan

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8242 ,  H01L29/51

CPC分类号： H01L21/28176 ,  H01L21/28194 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6656 ,  H01L29/6659

摘要： Methods are disclosed that fabricating semiconductor devices with high-k dielectric layers. The invention removes portions of deposited high-k dielectric layers not below gates and covers exposed portions (e.g., sidewalls) of high-k dielectric layers during fabrication with an encapsulation layer, which mitigates defects in the high-k dielectric layers and contamination of process tools. The encapsulation layer can also be employed as an etch stop layer and, at least partially, in comprising sidewall spacers. As a result, a semiconductor device can be fabricated with a substantially uniform equivalent oxide thickness.

摘要翻译： 公开了制造具有高k电介质层的半导体器件的方法。 本发明除了不在门下方的沉积的高k电介质层的部分，并且在用封装层制造期间覆盖高k电介质层的暴露部分（例如，侧壁），这减轻了高k电介质层中的缺陷和工艺污染 工具 封装层也可以用作蚀刻停止层，并且至少部分地包括侧壁间隔物。 结果，可以制造具有基本均匀的等效氧化物厚度的半导体器件。

公开(公告)号：US20050124121A1

公开(公告)日：2005-06-09

申请号：US10731647

申请日：2003-12-09

申请人： Antonio Rotondaro ,  James Chambers ,  Mark Visokay ,  Luigi Colombo

发明人： Antonio Rotondaro ,  James Chambers ,  Mark Visokay ,  Luigi Colombo

IPC分类号： C23C16/56 ,  H01L21/28 ,  H01L21/31 ,  H01L21/314 ,  H01L21/316 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/8242 ,  H01L29/51

CPC分类号： H01L21/02318 ,  C23C16/56 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/3143 ,  H01L21/31641 ,  H01L21/31645 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： The present invention pertains to annealing a high dielectric constant (high-k) material in a manner that substantially reduces or eliminates disadvantages and problems heretofore associated with the same. In particular, the high-k material is annealed in an ambient having a single chemistry of nitrogen and hydrogen, such as ammonia (NH3), to nitride and react unwanted impurities, and an oxidizer to oxidize and densify the high-k material, while mitigating growth of a lower-k material at an interface of the high-k material and an underlying substrate. Additionally, particular temperatures and pressures are utilized within the process so that the risk of an undesired exothermic reaction is mitigated. Annealing the high-k material in accordance with manners disclosed herein has application to semiconductor fabrication processes and, as such, is discussed herein within the context of the same.

摘要翻译： 本发明涉及以大大减少或消除与之相关的缺点和问题的方式退火高介电常数（高k）材料。 特别地，高k材料在具有氮和氢的单一化学性质（例如氨（NH 3））的环境中退火至氮化物并反应不需要的杂质，以及氧化剂氧化和 致密化高k材料，同时减轻在高k材料和下层衬底的界面处的较低k材料的生长。 此外，在该方法中利用特定的温度和压力，以便减轻不期望的放热反应的风险。 根据本文公开的方式对高k材料进行退火，已经应用于半导体制造工艺，并且因此本文在其上下文中讨论。

公开(公告)号：US20050101145A1

公开(公告)日：2005-05-12

申请号：US10703388

申请日：2003-11-06

申请人： Mark Visokay ,  Luigi Colombo

发明人： Mark Visokay ,  Luigi Colombo

IPC分类号： H01L21/302 ,  H01L21/461 ,  H01L21/8238

CPC分类号： H01L21/823842

摘要： Fabricating a semiconductor includes depositing a metal layer outwardly from a dielectric layer and forming a mask layer outwardly from a first portion of the metal layer. Atoms are incorporated into an exposed second portion of the metal layer to form a composition-altered portion of the metal layer. The mask layer is removed from the first portion of the metal layer and a barrier layer is deposited outwardly from the metal layer. A poly-Si layer is deposited outwardly from the barrier layer to form a semiconductor layer, where the barrier layer substantially prevents reaction of the metal layer with the poly-Si layer. The semiconductor layer is etched to form gate stacks, where each gate stack operates according to one of a plurality of work functions.

摘要翻译： 制造半导体包括从电介质层向外沉积金属层并从金属层的第一部分向外形成掩模层。 将原子并入金属层的暴露的第二部分中以形成金属层的组合物改变部分。 掩模层从金属层的第一部分去除，并且阻挡层从金属层向外沉积。 多晶硅层从阻挡层向外沉积形成半导体层，其中阻挡层基本上防止了金属层与多晶硅层的反应。 蚀刻半导体层以形成栅极堆叠，其中每个栅极堆叠根据多个功函数中的一个工作。

公开(公告)号：US06696332B2

公开(公告)日：2004-02-24

申请号：US10176596

申请日：2002-06-21

申请人： Mark Robert Visokay ,  Antonio Luis Pacheco Rotondaro ,  Luigi Colombo

发明人： Mark Robert Visokay ,  Antonio Luis Pacheco Rotondaro ,  Luigi Colombo

IPC分类号： H01L218238

CPC分类号： H01L21/28185 ,  H01L21/2652 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28238 ,  H01L21/28291 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： Methods are disclosed for forming gate dielectrics for MOSFET transistors, wherein a bilayer deposition of a nitride layer and an oxide layer are used to form a gate dielectric stack. The nitride layer is formed on the substrate to prevent oxidation of the substrate material during deposition of the oxide layer, thereby avoiding or mitigating formation of low-k interfacial layer.

摘要翻译： 公开了用于形成用于MOSFET晶体管的栅极电介质的方法，其中使用氮化物层和氧化物层的双层沉积来形成栅极电介质叠层。 在衬底上形成氮化物层以防止氧化物层沉积期间衬底材料的氧化，从而避免或减轻低k界面层的形成。

公开(公告)号：US06528386B1

公开(公告)日：2003-03-04

申请号：US10097919

申请日：2002-03-13

申请人： Scott R. Summerfelt ,  Luigi Colombo ,  Stephen R. Gilbert ,  Theodore S. Moise, IV ,  Sanjeev Aggarwal

发明人： Scott R. Summerfelt ,  Luigi Colombo ,  Stephen R. Gilbert ,  Theodore S. Moise, IV ,  Sanjeev Aggarwal

IPC分类号： H01L2176

CPC分类号： H01L27/11502 ,  H01L27/11507

摘要： A method of fabricating a ferroelectric capacitor is disclosed. The method comprises the patterning of a top electrode layer and a dielectric layer to form a capacitor stack structure having sidewalls associated therewith. Prior to patterning the bottom electrode layer, a protective film is formed on the sidewalls of the capacitor stack structure in order to protect the dielectric material from conductive contaminants associated with a subsequent patterning of the bottom electrode layer.

摘要翻译： 公开了一种制造铁电电容器的方法。 该方法包括图案化顶部电极层和电介质层以形成具有与其相关联的侧壁的电容器堆叠结构。 在图形化底部电极层之前，在电容器堆叠结构的侧壁上形成保护膜，以保护电介质材料免受与随后的底部电极层的图案化有关的导电污染物的影响。

公开(公告)号：US20130019399A1

公开(公告)日：2013-01-24

申请号：US13637778

申请日：2011-04-11

申请人： Luigi Colombo

发明人： Luigi Colombo

IPC分类号： A47C17/40 ,  A47B83/00

CPC分类号： A47C17/40

摘要： A pull-down bed assembly including a movable frame which constitutes the bedspring and is pivoted to a fixed frame so as to define a closed vertical position, in which the movable frame is substantially in a vertical position, and an open horizontal position, for use as a bed, in which the movable frame is in the horizontal position; the assembly has a balancing system, which is adapted to control the movement of the movable frame with respect to the fixed frame. The balancing system is constituted by springs with a respective transmission mechanism, which are arranged within the fixed frame and the movable frame and are not visible from the outside both in the closed position and in the open position of the movable frame.

摘要翻译： 一种下拉床组件，其包括构成床垫的可移动框架，并且枢转到固定框架，以便限定可闭合的框架基本处于垂直位置的闭合的垂直位置和用于使用的开放的水平位置 作为可移动框架处于水平位置的床; 组件具有平衡系统，其适于控制可移动框架相对于固定框架的移动。 平衡系统由具有各自的传动机构的弹簧构成，其布置在固定框架和可移动框架内，并且在关闭位置和可移动框架的打开位置都不能从外部看到。

公开(公告)号：US08309438B2

公开(公告)日：2012-11-13

申请号：US12706116

申请日：2010-02-16

申请人： Luigi Colombo ,  Robert M. Wallace ,  Rodney S. Ruoff

发明人： Luigi Colombo ,  Robert M. Wallace ,  Rodney S. Ruoff

IPC分类号： H01L21/20

CPC分类号： H01L21/02612 ,  H01L21/02527

摘要： A method and semiconductor device for synthesizing graphene using ion implantation of carbon. Carbon is implanted in a metal using ion implantation. After the carbon is distributed in the metal, the metal is annealed and cooled in order to precipitate the carbon from the metal to form a layer of graphene on the surface of the metal. The metal/graphene surface is then transferred to a dielectric layer in such a manner that the graphene layer is placed on top of the dielectric layer. The metal layer is then removed. Alternatively, recessed regions are patterned and etched in a dielectric layer located on a substrate. Metal is later formed in these recessed regions. Carbon is then implanted into the metal using ion implantation. The metal may then be annealed and cooled in order to precipitate the carbon from the metal to form a layer of graphene on the metal's surface.

摘要翻译： 一种使用碳的离子注入合成石墨烯的方法和半导体器件。 使用离子注入将碳注入金属中。 在碳分布在金属中之后，对金属进行退火和冷却，以便从金属沉淀碳以在金属表面上形成一层石墨烯。 然后将金属/石墨烯表面转移到电介质层，使得石墨烯层被放置在电介质层的顶部上。 然后去除金属层。 或者，凹陷区域被图案化并蚀刻在位于基底上的电介质层中。 金属后来形成在这些凹陷区域。 然后使用离子注入将碳注入到金属中。 然后可以对金属进行退火和冷却，以便从金属沉淀碳以在金属表面上形成一层石墨烯。

公开(公告)号：US07642146B2

公开(公告)日：2010-01-05

申请号：US11620447

申请日：2007-01-05

申请人： James Joseph Chambers ,  Mark Robert Visokay ,  Luigi Colombo

发明人： James Joseph Chambers ,  Mark Robert Visokay ,  Luigi Colombo

IPC分类号： H01L21/8238

CPC分类号： H01L21/823857 ,  H01L21/823842 ,  Y10S438/981

摘要： The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively form high-k dielectric layers within NMOS regions. An I/O dielectric layer is formed in core and I/O regions of a semiconductor device (506). The I/O dielectric layer is removed (508) from the core region of the device. A core dielectric layer is formed in the core region (510). A barrier layer is deposited and patterned to expose the NMOS devices of the core region (512). The core dielectric layer is removed from the core NMOS devices (514). A high-k dielectric layer is formed (514) over the core and I/O regions. Then, the high-k dielectric layer is removed (512) from PMOS regions/devices of the core region and the NMOS and PMOS regions/devices of the I/O region.

摘要翻译： 本发明通过提供在NMOS区内选择性地形成高k电介质层的制造方法来促进半导体制造。 在半导体器件（506）的芯和I / O区域中形成I / O电介质层。 从器件的芯区域去除（508）I / O电介质层。 在芯区域（510）中形成芯介质层。 屏蔽层被沉积并图案化以暴露核心区域（512）的NMOS器件。 从核心NMOS器件（514）去除芯介质层。 在核心和I / O区域上形成高k电介质层（514）。 然后，从核心区域的PMOS区域/器件和I / O区域的NMOS和PMOS区域/器件去除高k电介质层（512）。