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83 条记录 (耗时 0.039 秒)

    High K stack for non-volatile memory
    51.
    发明授权
    High K stack for non-volatile memory 有权
    高K堆栈用于非易失性存储器

    公开(公告)号：US07855114B2

    公开(公告)日：2010-12-21

    申请号：US12351553

    申请日：2009-01-09

    申请人： Wei Zheng ,  Mark Randolph ,  Hidehiko Shiraiwa

    发明人： Wei Zheng ,  Mark Randolph ,  Hidehiko Shiraiwa

    IPC分类号： H01L21/336 ,  H01L29/778

    CPC分类号： H01L29/792 ,  G11C16/0475 ,  H01L21/28273 ,  H01L21/28282

    摘要： A memory device may include a source region and a drain region formed in a substrate and a channel region formed in the substrate between the source and drain regions. The memory device may further include a first oxide layer formed over the channel region, the first oxide layer having a first dielectric constant, and a charge storage layer formed upon the first oxide layer. The memory device may further include a second oxide layer formed upon the charge storage layer, a layer of dielectric material formed upon the second oxide layer, the dielectric material having a second dielectric constant that is greater than the first dielectric constant, and a gate electrode formed upon the layer of dielectric material.

    摘要翻译： 存储器件可以包括形成在衬底中的源极区域和漏极区域以及形成在源极和漏极区域之间的衬底中的沟道区域。 存储器件还可以包括形成在沟道区上的第一氧化物层，第一氧化物层具有第一介电常数，以及形成在第一氧化物层上的电荷存储层。 存储器件还可以包括形成在电荷存储层上的第二氧化物层，形成在第二氧化物层上的介电材料层，介电材料具有大于第一介电常数的第二介电常数，以及栅电极 形成在电介质材料层上。

    Method for determining wordline critical dimension in a memory array and related structure
    53.
    发明授权
    Method for determining wordline critical dimension in a memory array and related structure 有权
    用于确定存储器阵列和相关结构中的字线临界尺寸的方法

    公开(公告)号：US07339222B1

    公开(公告)日：2008-03-04

    申请号：US11416551

    申请日：2006-05-03

    申请人： Meng Ding ,  Hidehiko Shiraiwa ,  Mark Randolph

    发明人： Meng Ding ,  Hidehiko Shiraiwa ,  Mark Randolph

    IPC分类号： H01L27/108

    CPC分类号： H01L27/115 ,  H01L27/11517 ,  Y10S257/905

    摘要： According to one exemplary embodiment, a method for fabricating a memory array includes forming a number of trenches in a substrate, where the trenches determine a number of wordline regions in the substrate, where each of the wordline regions is situated between two adjacent trenches, and where each of the wordline regions have a wordline region width. The memory array can be a flash memory array. The method further includes forming a number of bitlines in the substrate, where the bitlines are situated perpendicular to the trenches. The method further includes forming a dielectric region in each of the trenches. The method further includes forming a dielectric stack over the bitlines, wordline regions, and trenches. The method further includes forming a number of wordlines, where each wordline is situated over one of the wordline regions. The wordline region width determines an active wordline width of each of the wordlines.

    摘要翻译： 根据一个示例性实施例，一种用于制造存储器阵列的方法包括在衬底中形成多个沟槽，其中沟槽确定衬底中的多个字线区域，其中每个字线区域位于两个相邻的沟槽之间，以及 其中每个字线区域具有字线区域宽度。 存储器阵列可以是闪存阵列。 该方法还包括在衬底中形成多个位线，其中位线垂直于沟槽定位。 该方法还包括在每个沟槽中形成电介质区域。 该方法还包括在位线，字线区域和沟槽之间形成电介质叠层。 该方法还包括形成多个字线，其中每个字线位于一个字线区域上。 字线区域宽度决定每个字线的有效字线宽度。

    Method of forming ONO flash memory devices using low energy nitrogen implantation
    58.
    发明授权
    Method of forming ONO flash memory devices using low energy nitrogen implantation 有权
    使用低能氮注入形成ONO闪存器件的方法

    公开(公告)号：US06362051B1

    公开(公告)日：2002-03-26

    申请号：US09648361

    申请日：2000-08-25

    申请人： Jean Yang ,  Yider Wu ,  Hidehiko Shiraiwa ,  Mark Ramsbey

    发明人： Jean Yang ,  Yider Wu ,  Hidehiko Shiraiwa ,  Mark Ramsbey

    IPC分类号： H01L21336

    CPC分类号： H01L21/28202 ,  H01L21/26533 ,  H01L21/28282 ,  H01L21/3144 ,  H01L29/513 ,  H01L29/518

    摘要： A gate structure for an ONO flash memory device includes a first layer of silicon oxide on top of a semiconductor substrate, a second layer of silicon oxide, a layer of silicon nitride sandwiched between the two silicon oxide layers, and a control gate on top of the second layer of silicon oxide. Nitrogen is implanted into the first layer of silicon oxide at less than normal energy levels to reduce the amount of damage to the underlying semiconductor substrate. After low energy nitrogen implantation, the semiconductor structure is heated to anneal out the implant damage and to diffuse the implanted nitrogen to the substrate and silicon oxide interface to cause SiN bonds to be formed at that interface. The SiN bonds is desirable because they improve the bonding strength at the interface and the nitrogen remaining in the silicon oxide layer increases the oxide bulk reliability.

    摘要翻译： 用于ONO闪速存储器件的栅极结构包括在半导体衬底的顶部上的第一氧化硅层，第二层氧化硅，夹在两个氧化硅层之间的氮化硅层和位于两个氧化硅层之上的控制栅极 第二层氧化硅。 氮以低于正常能级注入到第一氧化硅层中以减少对下面的半导体衬底的损伤量。 在低能量氮注入之后，半导体结构被加热以退出注入损伤并将注入的氮扩散到衬底和氧化硅界面，以在该界面处形成SiN键。 SiN键是理想的，因为它们改善了界面处的结合强度，并且保留在氧化硅层中的氮增加了氧化物体的可靠性。

    Leakage reducing writeline charge protection circuit
    59.
    发明授权
    Leakage reducing writeline charge protection circuit 有权
    泄漏减少写命令充电保护电路

    公开(公告)号：US09196624B2

    公开(公告)日：2015-11-24

    申请号：US13545469

    申请日：2012-07-10

    申请人： Bradley Marc Davis ,  Mark W. Randolph ,  Sung-Yong Chung ,  Hidehiko Shiraiwa

    发明人： Bradley Marc Davis ,  Mark W. Randolph ,  Sung-Yong Chung ,  Hidehiko Shiraiwa

    IPC分类号： H01L21/336 ,  H01L27/115 ,  H01L21/28

    CPC分类号： H01L27/11521 ,  H01L21/28273

    摘要： Methods and systems of fabricating a wordline protection structure are described. As described, the wordline protection structure includes a polysilicon structure formed adjacent to a memory core region. The polysilicon structure includes first doped region positioned on a core side of the polysilicon structure and a second doped region positioned on a spine side of the polysilicon structure. An un-doped region positioned between the first and second doped regions. A conductive layer is formed on top of the polysilicon structure and arranged so that it does not contact the un-doped region at either the transition between the first doped region and the un-doped region or the second doped region and un-doped region.

    摘要翻译： 描述了制作字线保护结构的方法和系统。 如上所述，字线保护结构包括与存储器核心区域相邻形成的多晶硅结构。 多晶硅结构包括位于多晶硅结构的芯侧的第一掺杂区和位于多晶硅结构的脊侧的第二掺杂区。 位于第一和第二掺杂区域之间的未掺杂区域。 导电层形成在多晶硅结构的顶部，并且被布置成使得其在第一掺杂区域和未掺杂区域或第二掺杂区域和未掺杂区域之间的过渡处不接触未掺杂区域。