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    TONE INVERSION WITH PARTIAL UNDERLAYER ETCH
    51.
    发明申请
    TONE INVERSION WITH PARTIAL UNDERLAYER ETCH 失效
    带有部分底层蚀刻的色调

    公开(公告)号：US20120126358A1

    公开(公告)日：2012-05-24

    申请号：US12952248

    申请日：2010-11-23

    申请人： John C. Arnold ,  Sean D. Burns ,  Matthew E. Colburn ,  Steven J. Holmes ,  Yunpeng Yin

    发明人： John C. Arnold ,  Sean D. Burns ,  Matthew E. Colburn ,  Steven J. Holmes ,  Yunpeng Yin

    IPC分类号： H01L21/311 ,  H01L23/00 ,  H01L21/768

    CPC分类号： H01L23/00 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for tone inversion for integrated circuit fabrication includes providing a substrate with an underlayer on top of the substrate; creating a first pattern, the first pattern being partially etched into a portion of the underlayer such that a remaining portion of the underlayer is protected and forms a second pattern, and such that the first pattern does not expose the substrate located underneath the underlayer; covering the first pattern with a layer of image reverse material (IRM); and etching the second pattern into the substrate. A structure for tone inversion for integrated circuit fabrication includes a substrate; a partially etched underlayer comprising a first pattern located over the substrate, the first pattern being partially etched into a portion of the underlayer such that a remaining portion of the underlayer is protected and forms a second pattern, and such that the first pattern does not expose the substrate located underneath the underlayer; and an image reversal material (IRM) layer located over the partially etched underlayer.

    摘要翻译： 用于集成电路制造的色调反转的方法包括：在衬底的顶部上提供具有底层的衬底; 产生第一图案，所述第一图案被部分地蚀刻到所述底层的一部分中，使得所述底层的剩余部分被保护并形成第二图案，并且使得所述第一图案不暴露位于所述底层下方的所述基板; 用一层图像反向材料（IRM）覆盖第一个图案; 并将第二图案刻蚀成衬底。 用于集成电路制造的色调反转的结构包括：衬底; 部分蚀刻的底层包括位于所述衬底上方的第一图案，所述第一图案被部分地蚀刻到所述底层的一部分中，使得所述底层的剩余部分被保护并形成第二图案，并且使得所述第一图案不暴露 底层位于底层下方; 以及位于部分蚀刻的底层上方的图像反转材料（IRM）层。

    METHOD FOR FORMING AN INTERCONNECT STRUCTURE
    52.
    发明申请
    METHOD FOR FORMING AN INTERCONNECT STRUCTURE 有权
    形成互连结构的方法

    公开(公告)号：US20120058640A1

    公开(公告)日：2012-03-08

    申请号：US12876510

    申请日：2010-09-07

    申请人： Ryoung-Han Kim ,  Matthew E. Colburn

    发明人： Ryoung-Han Kim ,  Matthew E. Colburn

    IPC分类号： H01L21/768

    CPC分类号： H01L21/76816 ,  H01L21/0337 ,  H01L21/31144

    摘要： A method for forming an interconnect structure includes forming a mandrel above a base layer, forming spacers on the mandrel, forming recesses in the base layer using the spacers as an etch template, and forming a conductive material in the recesses.

    摘要翻译： 用于形成互连结构的方法包括在基底层上形成心轴，在心轴上形成间隔物，使用间隔物作为蚀刻模板在基底层中形成凹陷，并在凹部中形成导电材料。

    Mask and etch process for pattern assembly
    53.
    发明授权
    Mask and etch process for pattern assembly 有权
    掩模和蚀刻工艺用于图案组装

    公开(公告)号：US08119531B1

    公开(公告)日：2012-02-21

    申请号：US13013935

    申请日：2011-01-26

    申请人： John C. Arnold ,  Sean D. Burns ,  Matthew E. Colburn ,  Yunpeng Yin

    发明人： John C. Arnold ,  Sean D. Burns ,  Matthew E. Colburn ,  Yunpeng Yin

    IPC分类号： H01L21/311

    CPC分类号： H01L21/0337 ,  H01L21/0331

    摘要： A method of forming a trench is provided that includes providing a stack having a semiconductor layer or dielectric layer, a metal nitride layer, a leveling layer, and a first mask layer. First trenches are etched through the first mask layer and the leveling layer. The first mask layer is removed. A second mask layer is formed on the leveling layer. Second trenches are formed through the second mask layer, wherein the base of the second trenches do not extend through the metal nitride layer. The second mask layer is removed. Exposed portions of the metal nitride layer are etched selectively to the semiconductor layer and remaining portions of the leveling layer to extend the first trenches and the second trenches into contact with an upper surface of the semiconductor layer.

    摘要翻译： 提供一种形成沟槽的方法，其包括提供具有半导体层或电介质层的叠层，金属氮化物层，流平层和第一掩模层。 通过第一掩模层和流平层蚀刻第一沟槽。 第一个掩模层被去除。 在平整层上形成第二掩模层。 通过第二掩模层形成第二沟槽，其中第二沟槽的基极不延伸穿过金属氮化物层。 去除第二掩模层。 金属氮化物层的暴露部分被选择性地蚀刻到半导体层和平整层的剩余部分，以使第一沟槽和第二沟槽延伸与半导体层的上表面接触。

    DUAL EXPOSURE TRACK ONLY PITCH SPLIT PROCESS
    56.
    发明申请
    DUAL EXPOSURE TRACK ONLY PITCH SPLIT PROCESS 有权
    双重接触跟踪只能分离分离过程

    公开(公告)号：US20110049680A1

    公开(公告)日：2011-03-03

    申请号：US12551801

    申请日：2009-09-01

    申请人： Sean D. Burns ,  Matthew E. Colburn ,  Steven J. Holmes

    发明人： Sean D. Burns ,  Matthew E. Colburn ,  Steven J. Holmes

    IPC分类号： H01L29/06 ,  G03F7/20 ,  H01L21/461

    CPC分类号： H01L21/31144 ,  G03F7/0035 ,  H01L21/0271 ,  H01L21/0338

    摘要： An integrated circuit is formed with structures spaced more closely together than a transverse dimension of such structures, such as for making contacts to electronic elements formed at minimum lithographically resolvable dimensions by dark field split pitch techniques. Acceptable overlay accuracy and process efficiency and throughput for the split pitch process that requires etching of a hard mark for each of a plurality of sequentially applied and patterned resist layers is supported by performing the etching of the hard mask entirely within a lithography track through using an acid sensitive hard mark material and an acidic overcoat which contacts areas of the hard mask through patterned apertures in the resist. The contacted areas of the hard mask are activated for development by baking of the acidic overcoat.

    摘要翻译： 集成电路形成为具有比这种结构的横向尺寸更紧密地在一起的结构，例如用于通过暗场分割俯仰技术以最小可光滑分辨尺寸形成的电子元件的接触。 对于需要蚀刻多个顺序施加的和图案化的抗蚀剂层中的每一个的硬标记的分割间距处理的可接受的覆盖精度和处理效率和处理量通过使用 酸敏感的硬标记材料和通过抗蚀剂中的图案化孔接触硬掩模的区域的酸性外涂层。 通过烘烤酸性外涂层来激活硬掩模的接触区域以进行显影。

    Method and materials for patterning a neutral surface
    58.
    发明授权
    Method and materials for patterning a neutral surface 有权
    用于图案化中性面的方法和材料

    公开(公告)号：US07790350B2

    公开(公告)日：2010-09-07

    申请号：US11882163

    申请日：2007-07-30

    申请人： Gregory Breyta ,  Matthew E. Colburn

    发明人： Gregory Breyta ,  Matthew E. Colburn

    IPC分类号： G03F7/00 ,  G03F7/004

    CPC分类号： H01L21/31144 ,  B82Y10/00 ,  H01L21/7682

    摘要： A self assembly step for the manufacture of an electronic component comprising, e.g., a semiconductor chip or semiconductor array or wafer comprises forming a block copolymer film placed on a random copolymer film substrate operatively associated with the electronic component and the block copolymer film wherein the surface energy of the random copolymer film is tailored by use of a photolithographic or chemical process prior to the self assembly step. By prior deterministic control over regional surface properties of the random copolymer film, domains of the block copolymer film form only in predefined areas. This approach offers simplified processing and a precise control of regions where domain formation occurs. Selective removal of some of the domains allows for further processing of the electronic component.

    摘要翻译： 用于制造包括例如半导体芯片或半导体阵列或晶片的电子部件的自组装步骤包括形成位于与电子部件和嵌段共聚物膜操作相关的无规共聚物膜基材上的嵌段共聚物膜，其中表面 在自组装步骤之前，通过使用光刻或化学方法来调整无规共聚物膜的能量。 通过对无规共聚物膜的区域表面性质的先前确定性控制，嵌段共聚物膜的畴仅形成在预定区域中。 这种方法提供简化的处理和精确控制域形成发生的区域。 某些域的选择性删除允许进一步处理电子元件。

    Gate patterning scheme with self aligned independent gate etch
    60.
    发明授权
    Gate patterning scheme with self aligned independent gate etch 失效
    具有自对准独立栅极蚀刻的栅极图案化方案

    公开(公告)号：US07749903B2

    公开(公告)日：2010-07-06

    申请号：US12027444

    申请日：2008-02-07

    申请人： Scott D. Halle ,  Matthew E. Colburn ,  Bruce B. Doris ,  Thomas W. Dyer

    发明人： Scott D. Halle ,  Matthew E. Colburn ,  Bruce B. Doris ,  Thomas W. Dyer

    IPC分类号： H01L21/44

    CPC分类号： H01L21/32139 ,  H01L21/266 ,  H01L21/28123 ,  H01L21/823828

    摘要： A method for self-aligned gate patterning is disclosed. Two masks are used to process adjacent semiconductor components, such as an nFET and pFET that are separated by a shallow trench isolation region. The mask materials are chosen to facilitate selective etching. The second mask is applied while the first mask is still present, thereby causing the second mask to self align to the first mask. This avoids the undesirable formation of a stringer over the shallow trench isolation region, thereby improving the yield of a semiconductor manufacturing operation.

    摘要翻译： 公开了一种用于自对准栅极图案化的方法。 使用两个掩模来处理相邻的半导体部件，例如由浅沟槽隔离区分隔的nFET和pFET。 选择掩模材料以便于选择性蚀刻。 当第一掩模仍然存在时，施加第二掩模，从而使第二掩模与第一掩模自对准。 这避免了在浅沟槽隔离区域上不期望地形成纵梁，从而提高半导体制造操作的产量。