公开(公告)号：US11295797B1

公开(公告)日：2022-04-05

申请号：US17103552

申请日：2020-11-24

Applicant: Micron Technology, Inc.

Inventor： Angelo Visconti

IPC: G11C11/22

Abstract: Methods, systems, and devices for techniques to mitigate asymmetric long delay stress are described. A memory device may activate a memory cell during a first phase of an access operation cycle. The memory device may write a first state or a second state to the memory cell during the first phase of the access operation cycle. The memory device may maintain the first state or the second state during a second phase of the access operation cycle after the first phase of the access operation cycle. The memory device may write, during a third phase of the access operation cycle after the second phase of the access operation cycle, the second state to the memory cell. The memory device may precharge the memory cell during the third phase of the access operation cycle based on writing the second state to the memory cell.

公开(公告)号：US20220020412A1

公开(公告)日：2022-01-20

申请号：US17362348

申请日：2021-06-29

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Umberto Di Vincenzo ,  Riccardo Muzzetto ,  Angelo Visconti

IPC: G11C11/22 ,  G11C7/06

Abstract: Methods, systems, and devices for read operations based on a dynamic reference are described. A memory device may include a set of memory cells each associated with a capacitive circuit including a first and second capacitor. After receiving a read command, the memory device may couple each capacitive circuit with a respective memory cell (e.g., to transfer a charge stored by each respective memory cell to a capacitive circuit) and may couple the second capacitor of each capacitive circuit to a reference voltage bus. Thus, a reference voltage on the reference voltage bus may be based on an average charge across the second capacitors of each capacitive circuit. The memory device may then compare a charge stored by the first and second capacitors of each capacitive circuit with the reference voltage bus and may output a set of values stored by the set of memory cells based on the comparing.

公开(公告)号：US20210311824A1

公开(公告)日：2021-10-07

申请号：US16840286

申请日：2020-04-03

Applicant: Micron Technology, Inc.

Inventor： Richard E. Fackenthal ,  Angelo Visconti

IPC: G06F11/10 ,  G11C11/22 ,  G11C11/4091

Abstract: Methods, systems, and devices for erasure decoding for a memory device are described. In accordance with the described techniques, a memory device may be configured to identify conditions associated with an erasure, a possible erasure, or an otherwise indeterminate logic state (e.g., of a memory cell, of an information position of a codeword). Such an identification may be used to enhance aspects of error handling operations, including those that may be performed at the memory device or a host device (e.g., error handling operations performed at a memory controller external to the memory device). For example, error handling operations may be performed using speculative codewords, where information positions associated with an indeterminate or unassigned logic state are assigned with a respective assumed logic state, which may extend a capability of error detection or error correction compared to handling errors with unknown positions.

公开(公告)号：US20210210130A1

公开(公告)日：2021-07-08

申请号：US17208470

申请日：2021-03-22

Applicant: Micron Technology, Inc.

Inventor： Angelo Visconti

IPC: G11C11/22 ,  G11C11/4091

Abstract: Methods, systems, and devices for memory management associated with charge leakage in a memory device are described. A memory device may identify a charge leakage associated with one or more memory cells or access lines, and may determine whether to invert a logic state stored by a memory cell or a set of memory cells to improve the likelihood that the memory cells are read properly in the presence of charge leakage. In some examples, the memory device may also store an indication that the complement of the detected logic state was written, such as a bit flip indication, which may correspond to one memory cell or a set of memory cells.

公开(公告)号：US10964372B2

公开(公告)日：2021-03-30

申请号：US16441763

申请日：2019-06-14

Applicant: Micron Technology, Inc.

Inventor： Angelo Visconti ,  Giorgio Servalli ,  Andrea Locatelli

IPC: G11C11/22 ,  G06F3/06

Abstract: Methods, systems, and devices for memory cell biasing techniques are described. A memory cell may be accessed during an access phase of an access operation. A pre-charge phase of the access phase may be initiated. The memory cell may be biased to a voltage (e.g., a non-zero voltage) after the pre-charge phase. In some examples, the memory cell may be biased to the voltage when a word line is unbiased and the memory cell is isolated from the digit line.

公开(公告)号：US20180308552A1

公开(公告)日：2018-10-25

申请号：US16019631

申请日：2018-06-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Silvia Beltrami ,  Angelo Visconti

IPC: G11C16/10 ,  G11C16/34 ,  G11C16/12

Abstract: Methods of operating a memory device include programming a page of a memory block of the memory device using a particular starting programming voltage, determining a programming voltage indicative of a programming efficiency of the page of the memory block during programming of the page of the memory block, storing a representation of the programming voltage indicative of the programming efficiency of the page of the memory block, setting a starting programming voltage for a different page of the memory block in response to the stored representation of the programming voltage indicative of the programming efficiency of the page of the memory block, and programming the different page of the memory block using its starting programming voltage.

公开(公告)号：US20160005473A1

公开(公告)日：2016-01-07

申请号：US14856105

申请日：2015-09-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Silvia Beltrami ,  Angelo Visconti

IPC: G11C16/10 ,  G11C16/34 ,  G11C16/26

CPC classification number: G11C16/10 ,  G11C16/12 ,  G11C16/3459 ,  G11C16/3463 ,  G11C16/3468 ,  G11C16/3486 ,  G11C16/3495

Abstract: Methods of operating a memory device include programming a page of a memory block of the memory device using a particular starting programming voltage, determining a programming voltage indicative of a programming efficiency of the page of the memory block during programming of the page of the memory block, storing a representation of the programming voltage indicative of the programming efficiency of the page of the memory block, setting a starting programming voltage for a different page of the memory block in response to the stored representation of the programming voltage indicative of the programming efficiency of the page of the memory block, and programming the different page of the memory block using its starting programming voltage.

Abstract translation: 操作存储器件的方法包括使用特定的起始编程电压对存储器件的存储器块的页面进行编程，在编程存储器块的页面期间确定指示存储器块的页面的编程效率的编程电压 存储指示存储器块的页面的编程效率的编程电压的表示，响应于所存储的表示编程效率的编程电压的表示来设置存储器块的不同页面的起始编程电压 存储器块的页面，并使用其启动编程电压对存储器块的不同页面进行编程。

公开(公告)号：US09142314B2

公开(公告)日：2015-09-22

申请号：US14301798

申请日：2014-06-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Silvia Beltrami ,  Angelo Visconti

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/34 ,  G11C16/10

CPC classification number: G11C16/10 ,  G11C16/12 ,  G11C16/3459 ,  G11C16/3463 ,  G11C16/3468 ,  G11C16/3486 ,  G11C16/3495

Abstract: Certain aspects of this disclosure relate to programming an at least one flash memory cell using an at least one programming pulse with a new programming voltage having a level. The level is maintained in at least one page in a block of a flash memory controller memory, wherein the level varies as a function of a number of programming cycles applied to the at least one flash memory cell.

Abstract translation: 本公开的某些方面涉及使用具有具有电平的新编程电压的至少一个编程脉冲来编程至少一个闪存单元。 该电平被维持在闪速存储器控制器存储器的块中的至少一个页面中，其中该电平根据应用于至少一个闪存单元的编程周期的数量而变化。

公开(公告)号：US20150114946A1

公开(公告)日：2015-04-30

申请号：US14584628

申请日：2014-12-29

Applicant: Micron Technology, Inc.

Inventor： Gian Pietro Vanalli ,  Stefano Corno ,  Giovanni Campardo ,  Angelo Visconti ,  Silvia Beltrami ,  Alexey Petrushin

IPC: G11C16/26 ,  H05B3/00

CPC classification number: G11C16/26 ,  G11C11/00 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3431 ,  H01L23/345 ,  H01L2924/0002 ,  H05B3/00 ,  H01L2924/00

Abstract: A memory controller can provide current to a heater in a flash memory to reduce cycling induced errors. If necessary, after heating, the memory may be refreshed. In non-battery powered systems, data may be removed from the memory prior to heating and restored to the memory after heating.

Abstract translation: 存储器控制器可以向闪存中的加热器提供电流以减少循环引起的误差。 如果需要，加热后，可以刷新存储器。 在非电池供电系统中，数据可能在加热之前从存储器中移除，并在加热后恢复到存储器。

公开(公告)号：US12300298B2

公开(公告)日：2025-05-13

申请号：US18047568

申请日：2022-10-18

Applicant: Micron Technology, Inc.

Inventor： Durai Vishak Nirmal Ramaswamy ,  Giorgio Servalli ,  Angelo Visconti ,  Marcello Mariani ,  Alessandro Calderoni

IPC: G11C11/22 ,  G11C7/06

Abstract: Methods, systems, and devices for differential storage in memory arrays are described. A memory device may include pairs of memory cells configured to store a single logic state (e.g., a single bit of information). Additionally, the memory device may include sense amplifiers configured to sense the logic state based on a difference between a voltage of a first ferroelectric memory cell of the pair of memory cells and a voltage of a second ferroelectric memory cell of the pair of memory cells. In one example, the memory device may include pairs of memory cells within a single memory array on a single level. Here, each memory cell pair may include a memory cells that are each coupled with a same word line and plate line. Additionally, each memory cell pair may include memory cells each coupled with different digit lines.