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公开(公告)号：US20160098223A1
公开(公告)日：2016-04-07
申请号：US14967934
申请日：2015-12-14
Applicant: Micron Technology, Inc.
Inventor： Federico Tiziani , Giovanni Campardo , Massimo Iaculo , Claudio Giaccio , Manuela Scognamiglio , Danilo Caraccio , Ornella Vitale , Antonino Pollio
CPC classification number: G06F3/0625 , G06F1/3275 , G06F3/0634 , G06F3/0659 , G06F3/0679 , G06F11/10 , G06F11/1044 , G06F11/1068 , G06F11/1072 , G06F12/0246 , G06F13/1668 , G11C29/52 , Y02D10/14
Abstract: A single virtualized ECC NAND controller executes an ECC algorithm and manages a stack of NAND flash memories. The virtualized ECC NAND controller allows the host processor to drive the stack of flash memory devices as a single NAND chip while the controller redirects the data to the selected NAND memory device in the stack.
Abstract translation: 单个虚拟化ECC NAND控制器执行ECC算法并管理NAND闪存堆栈。 虚拟化ECC NAND控制器允许主机处理器作为单个NAND芯片驱动闪存器件堆叠，同时控制器将数据重定向到堆栈中选择的NAND存储器件。
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公开(公告)号：US20150114946A1
公开(公告)日：2015-04-30
申请号：US14584628
申请日：2014-12-29
Applicant: Micron Technology, Inc.
Inventor： Gian Pietro Vanalli , Stefano Corno , Giovanni Campardo , Angelo Visconti , Silvia Beltrami , Alexey Petrushin
CPC classification number: G11C16/26 , G11C11/00 , G11C16/3418 , G11C16/3427 , G11C16/3431 , H01L23/345 , H01L2924/0002 , H05B3/00 , H01L2924/00
Abstract: A memory controller can provide current to a heater in a flash memory to reduce cycling induced errors. If necessary, after heating, the memory may be refreshed. In non-battery powered systems, data may be removed from the memory prior to heating and restored to the memory after heating.
Abstract translation: 存储器控制器可以向闪存中的加热器提供电流以减少循环引起的误差。 如果需要，加热后，可以刷新存储器。 在非电池供电系统中，数据可能在加热之前从存储器中移除，并在加热后恢复到存储器。
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公开(公告)号：US20140351675A1
公开(公告)日：2014-11-27
申请号：US14456559
申请日：2014-08-11
Applicant: Micron Technology, Inc.
Inventor： Federico Tiziani , Giovanni Campardo , Massimo Iaculo , Claudio Giaccio , Manuela Scognamiglio , Danilo Caraccio , Ornella Vitale , Antonino Pollio
CPC classification number: G06F3/0625 , G06F1/3275 , G06F3/0634 , G06F3/0659 , G06F3/0679 , G06F11/10 , G06F11/1044 , G06F11/1068 , G06F11/1072 , G06F12/0246 , G06F13/1668 , G11C29/52 , Y02D10/14
Abstract: In various embodiments, a single virtualized error correcting code (ECC) NAND controller executes an ECC algorithm and manages a stack of NAND flash memories. The virtualized ECC NAND controller allows the host processor to drive the stack of flash memory devices as a single NAND chip while the controller redirects the data to the selected NAND memory device in the stack. In various embodiments, a controller manages a plurality of NAND memory devices. The controller provides power to a select one of the plurality of NAND memory devices at a time to conserve overall power consumption of the storage system.
Abstract translation: 在各种实施例中，单个虚拟化纠错码（ECC）NAND控制器执行ECC算法并管理NAND闪存堆栈。 虚拟化ECC NAND控制器允许主机处理器作为单个NAND芯片驱动闪存器件堆叠，同时控制器将数据重定向到堆栈中选择的NAND存储器件。 在各种实施例中，控制器管理多个NAND存储器件。 控制器一次为多个NAND存储器件中的一个选择一个供电，以节省存储系统的整体功耗。
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公开(公告)号：US09971536B2
公开(公告)日：2018-05-15
申请号：US15431457
申请日：2017-02-13
Applicant: Micron Technology, Inc.
Inventor： Federico Tiziani , Giovanni Campardo , Massimo Iaculo , Claudio Giaccio , Manuela Scognamiglio , Danilo Caraccio , Ornella Vitale , Antonino Pollio
CPC classification number: G06F3/0625 , G06F1/3275 , G06F3/0634 , G06F3/0659 , G06F3/0679 , G06F11/10 , G06F11/1044 , G06F11/1068 , G06F11/1072 , G06F12/0246 , G06F13/1668 , G11C29/52 , Y02D10/14
Abstract: Various embodiments disclose a controller to manage memory devices. In an exemplary method, signals are exchanged with a host processor to allow the host processor to communicate with multiple memory devices in a memory stack as a single device, regardless of an actual number of memory devices within the memory stack. Power is provided to a single one of the multiple memory devices in the memory stack at a time to reduce power consumption. Other methods, apparatuses, and devices are also disclosed.
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公开(公告)号：US20170160973A1
公开(公告)日：2017-06-08
申请号：US15431457
申请日：2017-02-13
Applicant: Micron Technology, Inc.
Inventor： Federico Tiziani , Giovanni Campardo , Massimo Iaculo , Claudio Giaccio , Manuela Scognamiglio , Danilo Caraccio , Ornella Vitale , Antonino Pollio
CPC classification number: G06F3/0625 , G06F1/3275 , G06F3/0634 , G06F3/0659 , G06F3/0679 , G06F11/10 , G06F11/1044 , G06F11/1068 , G06F11/1072 , G06F12/0246 , G06F13/1668 , G11C29/52 , Y02D10/14
Abstract: A single virtualized ECC NAND controller executes an ECC algorithm and manages a stack of NAND flash memories. The virtualized ECC NAND controller allows the host processor to drive the stack of flash memory devices as a single NAND chip while the controller redirects the data to the selected NAND memory device in the stack.
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Patent Agency Ranking
公开(公告)号：US09569129B2
公开(公告)日：2017-02-14
申请号：US14967934
申请日：2015-12-14
Applicant: Micron Technology, Inc.
Inventor： Federico Tiziani , Giovanni Campardo , Massimo Iaculo , Claudio Giaccio , Manuela Scognamiglio , Danilo Caraccio , Ornella Vitale , Antonino Pollio
CPC classification number: G06F3/0625 , G06F1/3275 , G06F3/0634 , G06F3/0659 , G06F3/0679 , G06F11/10 , G06F11/1044 , G06F11/1068 , G06F11/1072 , G06F12/0246 , G06F13/1668 , G11C29/52 , Y02D10/14
Abstract: Various embodiments disclose a controller to manage memory devices. In an exemplary method, signals are exchanged with a host processor to allow the host processor to communicate with a plurality of memory devices in a memory stack as a single device, regardless of an actual number of memory devices within the memory stack. Power is provided to a single one of the plurality of the memory devices in the memory stack at a time to reduce power consumption. Other methods, apparatuses, and devices are also disclosed.
Abstract translation: 各种实施例公开了一种用于管理存储器件的控制器。 在示例性方法中，信号与主处理器交换，以允许主机处理器作为单个设备与存储器堆叠中的多个存储器件通信，而不管存储器堆栈内的实际数量的存储器件。 一次将功率提供给存储器堆叠中的多个存储器件中的单个存储器件，以降低功耗。 还公开了其它方法，装置和装置。
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公开(公告)号：US08880979B2
公开(公告)日：2014-11-04
申请号：US13907669
申请日：2013-05-31
Applicant: Micron Technology, Inc.
Inventor： Giovanni Campardo , Stefano Corno , Gian Pietro Vanalli , Manuela Scognamiglio , Danilo Caraccio , Federico Tiziani , Massimiliano Magni , Andrea Ghilardelli
CPC classification number: G11C29/42 , G06F11/1048 , G11C2029/0411
Abstract: A method and system are disclosed in which a first non-volatile memory includes blocks that store data, and a second memory that stores overhead information related to the blocks storing the data. The amount of the second memory storing the overhead information related to the at least one block of the plurality of blocks is varied.
Abstract translation: 公开了一种方法和系统，其中第一非易失性存储器包括存储数据的块和存储与存储数据的块有关的开销信息的第二存储器。 存储与多个块的至少一个块相关的开销信息的第二存储器的量是变化的。
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8.发明申请ERROR CORRECTING CODES FOR INCREASED STORAGE CAPACITY IN MULTILEVEL MEMORY DEVICES 有权在多个存储器件中增加存储容量的错误校正代码公开(公告)号：US20130191697A1
公开(公告)日：2013-07-25
申请号：US13712880
申请日：2012-12-12
Applicant: Micron Technology, Inc.
Inventor： Paolo Amato , Giovanni Campardo
CPC classification number: H03M13/05 , G11C2029/0411 , H03M13/15 , H03M13/152 , H03M13/256 , H03M13/27 , H03M13/29 , H03M13/2933 , H03M13/2936 , H03M13/41
Abstract: Embodiments of the present disclosure provide methods, systems, and apparatuses related to multilevel encoding with error correction. In some embodiments, data may be programmed and/or read from a matrix of nonvolatile memory cells with concatenated encoding/decoding schemes. In some embodiments, a calculation module may determine an actual bit per cell value of a given combination of parameters of a nonvolatile memory device. Still other embodiments may be described and claimed.
Abstract translation: 本公开的实施例提供了与具有纠错的多级编码相关的方法，系统和装置。 在一些实施例中，可以使用级联的编码/解码方案从非易失性存储器单元的矩阵中编程和/或读取数据。 在一些实施例中，计算模块可以确定非易失性存储器件的给定参数组合的每个单元值的实际位数。 可以描述和要求保护其他实施例。
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公开(公告)号：US09183941B2
公开(公告)日：2015-11-10
申请号：US14584628
申请日：2014-12-29
Applicant: Micron Technology, Inc.
Inventor： Gian Pietro Vanalli , Stefano Corno , Giovanni Campardo , Angelo Visconti , Silvia Beltrami , Alexey Petrushin
CPC classification number: G11C16/26 , G11C11/00 , G11C16/3418 , G11C16/3427 , G11C16/3431 , H01L23/345 , H01L2924/0002 , H05B3/00 , H01L2924/00
Abstract: A memory controller can provide current to a heater in a flash memory to reduce cycling induced errors. If necessary, after heating, the memory may be refreshed. In non-battery powered systems, data may be removed from the memory prior to heating and restored to the memory after heating.
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公开(公告)号：US09213603B2
公开(公告)日：2015-12-15
申请号：US14456559
申请日：2014-08-11
Applicant: Micron Technology, Inc.
Inventor： Federico Tiziani , Giovanni Campardo , Massimo Iaculo , Claudio Giaccio , Manuela Scognamiglio , Danilo Caraccio , Ornella Vitale , Antonino Pollio
CPC classification number: G06F3/0625 , G06F1/3275 , G06F3/0634 , G06F3/0659 , G06F3/0679 , G06F11/10 , G06F11/1044 , G06F11/1068 , G06F11/1072 , G06F12/0246 , G06F13/1668 , G11C29/52 , Y02D10/14
Abstract: In various embodiments, a single virtualized error correcting code (ECC) NAND controller executes an ECC algorithm and manages a stack of NAND flash memories. The virtualized ECC NAND controller allows the host processor to drive the stack of flash memory devices as a single NAND chip while the controller redirects the data to the selected NAND memory device in the stack. In various embodiments, a controller manages a plurality of NAND memory devices. The controller provides power to a select one of the plurality of NAND memory devices at a time to conserve overall power consumption of the storage system.
Abstract translation: 在各种实施例中，单个虚拟化纠错码（ECC）NAND控制器执行ECC算法并管理NAND闪存堆栈。 虚拟化ECC NAND控制器允许主机处理器作为单个NAND芯片驱动闪存器件堆叠，同时控制器将数据重定向到堆栈中选择的NAND存储器件。 在各种实施例中，控制器管理多个NAND存储器件。 控制器一次为多个NAND存储器件中的一个选择一个供电，以节省存储系统的整体功耗。
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