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    Segregation-based memory
    51.
    发明授权
    Segregation-based memory 有权

    公开(公告)号：US11869585B2

    公开(公告)日：2024-01-09

    申请号：US17331610

    申请日：2021-05-26

    Applicant: Micron Technology, Inc.

    Inventor： Mattia Boniardi ,  Agostino Pirovano ,  Innocenzo Tortorelli

    IPC: G11C13/00

    CPC classification number: G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/009

    Abstract: Methods, systems, and devices for operating memory cell(s) are described. A resistance of a storage element included in a memory cell may be programmed by applying a voltage to the memory cell that causes ion movement within the storage element, where the storage element remains in a single phase and has different resistivity based on a location of the ions within the storage element. In some cases, multiple of such storage elements may be included in a memory cell, where ions within the storage elements respond differently to electric pulses, and a non-binary logic value may be stored in the memory cell by applying a series of voltages or currents to the memory cell.

    Neural network memory with an array of variable resistance memory cells
    55.
    发明授权
    Neural network memory with an array of variable resistance memory cells 有权

    公开(公告)号：US11587612B2

    公开(公告)日：2023-02-21

    申请号：US16502978

    申请日：2019-07-03

    Applicant: Micron Technology, Inc.

    Inventor： Innocenzo Tortorelli

    IPC: G11C11/54 ,  G06K9/62 ,  G06N3/063 ,  G11C11/56 ,  G11C13/00

    Abstract: In an example, an apparatus can include an array of variable resistance memory cells and a neural memory controller coupled to the array of variable resistance memory cells and configured to apply a sub-threshold voltage pulse to a variable resistance memory cell of the array to change a threshold voltage of the variable resistance memory cell in an analog fashion from a voltage associated with a reset state to effectuate a first synaptic weight change; and apply additional sub-threshold voltage pulses to the variable resistance memory cell to effectuate each subsequent synaptic weight change.

    TECHNIQUES FOR FORMING SELF-ALIGNED MEMORY STRUCTURES
    56.
    发明申请
    TECHNIQUES FOR FORMING SELF-ALIGNED MEMORY STRUCTURES 有权

    公开(公告)号：US20230027799A1

    公开(公告)日：2023-01-26

    申请号：US17881274

    申请日：2022-08-04

    Applicant: Micron Technology, Inc.

    Inventor： Stephen W. Russell ,  Andrea Redaelli ,  Innocenzo Tortorelli ,  Agostino Pirovano ,  Fabio Pellizzer ,  Lorenzo Fratin

    IPC: H01L45/00 ,  H01L27/24

    Abstract: Methods, systems, and devices for techniques for forming self-aligned memory structures are described. Aspects include etching a layered assembly of materials including a first conductive material and a first sacrificial material to form a first set of channels along a first direction that creates a first set of sections. An insulative material may be deposited within each of the first set of channels and a second sacrificial material may be deposited onto the first set of sections and the insulating material. A second set of channels may be etched into the layered assembly of materials along a second direction that creates a second set of sections, where the second set of channels extend through the first and second sacrificial materials. Insulating material may be deposited in the second set of channels and the sacrificial materials removed leaving a cavity. A memory material may be deposited in the cavity.

    APPARATUSES INCLUDING MULTI-LEVEL MEMORY CELLS AND METHODS OF OPERATION OF SAME
    57.
    发明申请
    APPARATUSES INCLUDING MULTI-LEVEL MEMORY CELLS AND METHODS OF OPERATION OF SAME 有权

    公开(公告)号：US20220366974A1

    公开(公告)日：2022-11-17

    申请号：US17816612

    申请日：2022-08-01

    Applicant: Micron Technology, Inc.

    Inventor： Innocenzo Tortorelli ,  Russell L. Meyer ,  Agostino Pirovano ,  Andrea Redaelli ,  Lorenzo Fratin ,  Fabio Pellizzer

    IPC: G11C11/56 ,  G11C13/00

    Abstract: Disclosed herein is a memory cell including a memory element and a selector device. Data may be stored in both the memory element and selector device. The memory cell may be programmed by applying write pulses having different polarities and magnitudes. Different polarities of the write pulses may program different logic states into the selector device. Different magnitudes of the write pulses may program different logic states into the memory element. The memory cell may be read by read pulses all having the same polarity. The logic state of the memory cell may be detected by observing different threshold voltages when the read pulses are applied. The different threshold voltages may be responsive to the different polarities and magnitudes of the write pulses.

    Memory cells for storing operational data
    58.
    发明授权
    Memory cells for storing operational data 有权

    公开(公告)号：US11417398B2

    公开(公告)日：2022-08-16

    申请号：US17108783

    申请日：2020-12-01

    Applicant: Micron Technology, Inc.

    Inventor： Mattia Boniardi ,  Anna Maria Conti ,  Innocenzo Tortorelli

    IPC: G11C7/00 ,  G11C16/10 ,  G11C16/34 ,  G11C16/30 ,  G11C16/26

    Abstract: Methods, systems, and devices for memory cells for storing operational data are described. A memory device may include an array of memory cells with different sets of cells for storing data. A first set of memory cells may store data for operating the memory device, and the associated memory cells may each contain a chalcogenide storage element. A second set of memory cells may store host data. Some memory cells included in the first set may be programmed to store a first logic state and other memory cells in the first set may be left unprogrammed (and may represent a second logic state). Sense circuitry may be coupled with the array and may determine a value of data stored by the first set of memory cells.

    Techniques for programming a memory cell
    60.
    发明授权
    Techniques for programming a memory cell 有权

    公开(公告)号：US11302393B2

    公开(公告)日：2022-04-12

    申请号：US17024248

    申请日：2020-09-17

    Applicant: Micron Technology, Inc.

    Inventor： Hernan A. Castro ,  Innocenzo Tortorelli ,  Agostino Pirovano ,  Fabio Pellizzer

    IPC: G11C13/00 ,  G11C5/06

    Abstract: Techniques are provided for programming a self-selecting memory cell that stores a first logic state. To program the memory cell, a pulse having a first polarity may be applied to the cell, which may result in the memory cell having a reduced threshold voltage. During a duration in which the threshold voltage of the memory cell may be reduced (e.g., during a selection time), a second pulse having a second polarity (e.g., a different polarity) may be applied to the memory cell. Applying the second pulse to the memory cell may result in the memory cell storing a second logic state different than the first logic state.

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