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    TRANSISTORS HAVING ONE OR MORE DUMMY LINES WITH DIFFERENT COLLECTIVE WIDTHS COUPLED THERETO
    52.
    发明申请
    TRANSISTORS HAVING ONE OR MORE DUMMY LINES WITH DIFFERENT COLLECTIVE WIDTHS COUPLED THERETO 有权
    带有不同组合宽度的一个或多个DUMMY线的晶体管

    公开(公告)号：US20160071842A1

    公开(公告)日：2016-03-10

    申请号：US14478220

    申请日：2014-09-05

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Michael A. Smith ,  Vladimir Mikhalev

    IPC: H01L27/088 ,  H01L23/528 ,  H01L27/02 ,  H01L27/115

    CPC classification number: H01L27/11578 ,  H01L27/0207 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11582

    Abstract: In an embodiment, an array of transistors has a first line coupled to a first transistor. The first line extends over a second transistor that is successively adjacent to the first transistor and over a third transistor that is successively adjacent to the second transistor. A second line is coupled to the second transistor and extends over the third transistor. One or more first dummy lines are coupled to the first line and extend from the first transistor to the second transistor. One or more second dummy lines are coupled to the second line and extend from the second transistor to the third transistor. A collective width of the one or more first dummy lines is greater than a collective width of the one or more second dummy lines.

    Abstract translation: 在一个实施例中，晶体管阵列具有耦合到第一晶体管的第一线。 第一行延伸在与第一晶体管相连的第二晶体管上，以及连续相邻于第二晶体管的第三晶体管。 第二线耦合到第二晶体管并在第三晶体管上延伸。 一个或多个第一虚拟线耦合到第一线并且从第一晶体管延伸到第二晶体管。 一个或多个第二虚拟线耦合到第二线并且从第二晶体管延伸到第三晶体管。 一个或多个第一虚拟线的总体宽度大于一个或多个第二虚拟线的总体宽度。

    Integrated Circuitry and Methods of Forming Transistors
    54.
    发明申请
    Integrated Circuitry and Methods of Forming Transistors 有权
    集成电路和形成晶体管的方法

    公开(公告)号：US20140339620A1

    公开(公告)日：2014-11-20

    申请号：US13897047

    申请日：2013-05-17

    Applicant: Micron Technology, Inc.

    Inventor： Michael A. Smith

    IPC: H01L27/115

    CPC classification number: H01L21/823418 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/823412 ,  H01L21/823456 ,  H01L21/82385 ,  H01L27/0207 ,  H01L27/0617 ,  H01L27/085 ,  H01L27/088 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11531 ,  H01L27/11573 ,  H01L29/063 ,  H01L29/0653 ,  H01L29/0873 ,  H01L29/66575 ,  H01L29/66659 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7833 ,  H01L29/7835 ,  H01L29/788 ,  H01L29/792

    Abstract: Some embodiments include integrated circuits having first and second transistors. The first transistor is wider than the second transistor. The first and second transistors have first and second active regions, respectively. Dielectric features are associated with the first active region and break up the first active region. The second active region is not broken up to the same extent as the first active region. Some embodiments include methods of forming transistors. Active areas of first and second transistors are formed. The active area of the first transistor is wider than the active area of the second transistor. Dielectric features are formed in the active area of the first transistor. The active area of the first transistor is broken up to a different extent than the active area of the second transistor. The active areas of the first and second transistors are simultaneously doped.

    Abstract translation: 一些实施例包括具有第一和第二晶体管的集成电路。 第一晶体管比第二晶体管宽。 第一和第二晶体管分别具有第一和第二有源区。 电介质特征与第一有源区相关联并且分解第一有源区。 第二活性区域不会分解成与第一活性区域相同的程度。 一些实施例包括形成晶体管的方法。 形成第一和第二晶体管的有效区域。 第一晶体管的有效面积比第二晶体管的有效面积宽。 电介质特征形成在第一晶体管的有源区中。 第一晶体管的有效面积被分解为与第二晶体管的有效面积不同的程度。 第一和第二晶体管的有源区同时掺杂。

    High voltage isolation devices for semiconductor devices
    56.
    发明授权
    High voltage isolation devices for semiconductor devices 有权

    公开(公告)号：US12278286B2

    公开(公告)日：2025-04-15

    申请号：US18406827

    申请日：2024-01-08

    Applicant: Micron Technology, Inc.

    Inventor： Michael A. Smith

    IPC: H01L29/78 ,  H01L29/10

    Abstract: High voltage isolation devices for semiconductor devices and associated systems, are disclosed herein. The isolation device may support operations of a 3-dimensional NAND memory array of the semiconductor device. In some embodiments, during high voltage operations (e.g., erase operations), the isolation device may provide a high voltage to the memory array while isolating other circuitry supporting low voltage operations of the memory array from the high voltage. The isolation device may include a set of narrow active areas separating the low voltage circuitry from the high voltage and a gate over the narrow active areas. In a further embodiment, the isolation device includes interdigitated narrow active areas and a common gate over the interdigitated narrow active areas to reduce an area occupied by the isolation devices.

    Active protection circuits for semiconductor devices
    57.
    发明授权
    Active protection circuits for semiconductor devices 有权

    公开(公告)号：US12237278B2

    公开(公告)日：2025-02-25

    申请号：US18142992

    申请日：2023-05-03

    Applicant: Micron Technology, Inc.

    Inventor： Michael A. Smith ,  Kenneth W. Marr

    IPC: H01L23/60 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

    Abstract: Active protection circuits for semiconductor devices, and associated systems and methods, are disclosed herein. The active protection circuits may protect various components of the semiconductor devices from process induced damage—e.g., stemming from process charging effects. In some embodiments, the active protection circuit includes an FET and a resistor coupled to certain nodes (e.g., source plates for 3D NAND memory arrays) of the semiconductor devices, which may be prone to accumulate the process charging effects. The active protection circuits prevent the nodes from reaching a predetermined voltage during process steps utilizing charged particles. Subsequently, metal jumpers may be added to the active protection circuits to deactivate the FETs for normal operations of the semiconductor devices. Further, the FET and the resistor of the active protection circuit may be integrated with an existing component of the semiconductor device.

    STRING DRIVER WITH THROUGH SILICON ISOLATION
    58.
    发明公开
    STRING DRIVER WITH THROUGH SILICON ISOLATION 审中-公开

    公开(公告)号：US20240290787A1

    公开(公告)日：2024-08-29

    申请号：US18424766

    申请日：2024-01-27

    Applicant: Micron Technology, Inc.

    Inventor： Michael A. Smith

    IPC: H01L27/092 ,  H01L21/762 ,  H01L23/00 ,  H01L23/528 ,  H10B80/00

    CPC classification number: H01L27/092 ,  H01L21/76224 ,  H01L23/5286 ,  H01L24/08 ,  H10B80/00 ,  H01L2224/08145

    Abstract: A string driver device including a substrate; and a plurality of string driver array blocks that are disposed above the substrate, each of the plurality of string driver array blocks including a plurality of active regions that are parallelly aligned along a length direction, a plurality of shared gates that are disposed above the plurality of active regions and along a width direction, the width direction being perpendicular to the length direction, a through silicon isolation (TSI) region that surrounds the plurality of active regions on the substrate and that is disposed between neighboring active regions of the plurality of active regions, and a plurality of shallow trench isolation (STI) regions that are disposed adjacent to one or more channel regions of each of the plurality of active regions and below the plurality of shared gates respectively.

    Reduced pitch memory subsystem for memory device
    59.
    发明授权
    Reduced pitch memory subsystem for memory device 有权

    公开(公告)号：US11973031B2

    公开(公告)日：2024-04-30

    申请号：US18083445

    申请日：2022-12-16

    Applicant: Micron Technology, Inc.

    Inventor： Michael A. Smith ,  Haitao Liu ,  Vladimir Mikhalev

    IPC: H01L23/528 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H10B10/00

    CPC classification number: H01L23/528 ,  H01L21/823885 ,  H01L27/092 ,  H01L29/66666 ,  H01L29/78 ,  H01L29/7827 ,  H10B10/12

    Abstract: A memory device includes an array of memory cells and a plurality of bit-lines with each bit-line connected to a respective set of memory cells of the array of memory cells. The memory device includes a memory subsystem having first and second memory circuits. Each first memory circuit can be disposed laterally adjacent to a second memory circuit. Each first memory circuit includes a first bit-line connection and each second memory circuit including a second bit-line connection, the first and second bit-line connections can connect to respective bit-lines. Each first bit-line connection is disposed on a first bit-line connection line of the memory subsystem and each second bit-line connection is disposed on a second bit-line connection line of the memory subsystem, and the second bit-line connection line can be offset from the first bit-line connection line by a predetermined distance that is greater than zero.

    Interleaved string drivers, string driver with narrow active region, and gated LDD string driver
    60.
    发明授权
    Interleaved string drivers, string driver with narrow active region, and gated LDD string driver 有权

    公开(公告)号：US11783896B2

    公开(公告)日：2023-10-10

    申请号：US17401239

    申请日：2021-08-12

    Applicant: Micron Technology, Inc.

    Inventor： Michael A. Smith ,  Martin W. Popp

    IPC: G11C16/14 ,  G11C16/08 ,  H01L29/78 ,  H01L29/10 ,  G11C16/04

    CPC classification number: G11C16/08 ,  G11C16/0483 ,  H01L29/1083 ,  H01L29/7833

    Abstract: A memory device includes a first string driver circuit and a second string driver circuit that are disposed laterally adjacent to each other in a length direction of a memory subsystem. The first and the second string driver circuits are disposed in an interleaved layout configuration such that the first connections of the first string driver are offset from the second connections of the second string driver in a width direction. For a same effective distance between the corresponding opposing first and second connections, a first pitch length corresponding to the interleaved layout configuration of the first and second string drivers is less by a predetermined reduction amount than a second pitch length between the first and second string drivers when disposed in a non-interleaved layout configuration in which each of the first connections is in-line with the corresponding second connection.

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