公开(公告)号：US20170025160A1

公开(公告)日：2017-01-26

申请号：US15287980

申请日：2016-10-07

Applicant: Micron Technology, Inc.

Inventor： Troy A. Manning

IPC: G11C7/06 ,  G11C7/10 ,  G11C7/12

CPC classification number: G11C7/065 ,  G11C7/06 ,  G11C7/062 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/1048 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4096 ,  G11C15/043

Abstract: The present disclosure includes apparatuses and methods related to performing compare and/or report operations using sensing circuitry. An example method can include charging an input/output (IO) line of a memory array to a voltage. The method can include determining whether data stored in the memory array matches a compare value. The determination of whether data stored matches a compare value can include activating a number of access lines of the memory array. The determination can include sensing a number of memory cells coupled to the number of access lines. The determination can include sensing whether the voltage of the IO line changes in response to activation of selected decode lines corresponding to the number of memory cells.

Abstract translation: 本公开包括与使用感测电路执行比较和/或报告操作相关的装置和方法。 示例性方法可以包括将存储器阵列的输入/输出（IO）线充电到电压。 该方法可以包括确定存储在存储器阵列中的数据是否与比较值相匹配。 确定存储的数据是否与比较值匹配可以包括激活存储器阵列的多个访问线。 该确定可以包括感测耦合到接入线路数量的多个存储器单元。 该确定可以包括检测IO线的电压是否响应于对应于存储器单元的数量的所选择的解码线的激活而改变。

公开(公告)号：US09530475B2

公开(公告)日：2016-12-27

申请号：US14854418

申请日：2015-09-15

Applicant: Micron Technology, Inc.

Inventor： Troy A. Manning

IPC: G11C7/00 ,  G11C8/10 ,  G06F12/08 ,  G06F13/40 ,  G06F9/30 ,  G11C11/419 ,  G06F12/02 ,  G06F12/06 ,  G11C8/12 ,  G11C7/10 ,  G11C7/06 ,  G11C11/408 ,  G11C11/4091

CPC classification number: G11C8/10 ,  G06F9/30 ,  G06F12/0246 ,  G06F12/0646 ,  G06F12/0888 ,  G06F13/40 ,  G06F2212/7202 ,  G11C7/06 ,  G11C7/1006 ,  G11C8/12 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/419 ,  G11C15/04 ,  G11C2207/2245 ,  Y02D10/13

Abstract: Examples of the present disclosure provide devices and methods for accessing a memory array address space. An example memory array comprising a first address space comprising memory cells coupled to a first number of select lines and to a number of sense lines and a second address space comprising memory cells coupled to a second number of select lines and to the number of sense lines. The first address space is independently addressable relative to the second address space.

公开(公告)号：US20160372177A1

公开(公告)日：2016-12-22

申请号：US15256066

申请日：2016-09-02

Applicant: Micron Technology, Inc.

Inventor： Troy A. Manning

IPC: G11C11/4091 ,  G11C11/4096 ,  G11C11/4093 ,  G11C11/408

CPC classification number: G11C11/4091 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/1012 ,  G11C11/4087 ,  G11C11/4093 ,  G11C11/4096 ,  G11C29/42

Abstract: The present disclosure includes apparatuses and methods related to determining an XOR value in memory. An example method can include performing a NAND operation on a data value stored in a first memory cell and a data value stored in a second memory cell. The method can include performing an OR operation on the data values stored in the first and second memory cells. The method can include performing an AND operation on the result of the NAND operation and a result of the OR operation without transferring data from the memory array via an input/output (I/O) line.

公开(公告)号：US09455020B2

公开(公告)日：2016-09-27

申请号：US14715161

申请日：2015-05-18

Applicant: Micron Technology, Inc.

Inventor： Troy A. Manning

IPC: G11C11/4091 ,  G11C7/06 ,  G11C7/10 ,  G11C11/4093

CPC classification number: G11C11/4091 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/1012 ,  G11C11/4087 ,  G11C11/4093 ,  G11C11/4096 ,  G11C29/42

Abstract: The present disclosure includes apparatuses and methods related to determining an XOR value in memory. An example method can include performing a NAND operation on a data value stored in a first memory cell and a data value stored in a second memory cell. The method can include performing an OR operation on the data values stored in the first and second memory cells. The method can include performing an AND operation on the result of the NAND operation and a result of the OR operation without transferring data from the memory array via an input/output (I/O) line.

Abstract translation: 本公开包括与确定存储器中的异或值相关的装置和方法。 示例性方法可以包括对存储在第一存储器单元中的数据值和存储在第二存储器单元中的数据值执行NAND操作。 该方法可以包括对存储在第一和第二存储器单元中的数据值执行或运算。 该方法可以包括对NAND操作的结果执行AND运算和OR运算的结果，而不经由输入/输出（I / O）线从存储器阵列传送数据。

公开(公告)号：US09298545B2

公开(公告)日：2016-03-29

申请号：US14255064

申请日：2014-04-17

Applicant: Micron Technology, Inc.

Inventor： Sampath K. Ratnam ,  Troy D. Larsen ,  Doyle W. Rivers ,  Troy A. Manning ,  Martin L. Culley

IPC: G11C29/00 ,  G06F11/10 ,  G11C11/56 ,  G11C16/04

CPC classification number: G06F11/1068 ,  G06F11/10 ,  G06F11/108 ,  G11C11/5628 ,  G11C16/0483

Abstract: Data protection across multiple memory blocks can include writing a first portion of a codeword in a first location of a first memory block and writing a second portion of the codeword in a second location of a second memory block. The second location of the second memory block can be different than the first location of the first memory block.

Abstract translation: 跨越多个存储器块的数据保护可以包括将码字的第一部分写入第一存储器块的第一位置，并将码字的第二部分写入第二存储器块的第二位置。 第二存储器块的第二位置可以不同于第一存储器块的第一位置。

公开(公告)号：US20250029651A1

公开(公告)日：2025-01-23

申请号：US18763330

申请日：2024-07-03

Applicant: Micron Technology, Inc.

Inventor： Glen E. Hush ,  Troy A. Manning ,  Timothy P. Finkbeiner ,  Troy D. Larsen ,  Peter L. Brown

IPC: G11C11/4091 ,  G11C11/408 ,  H03K19/20

Abstract: Methods, systems, and devices related to performing logical operations using multiple digit lines. At least two digit lines coupled to the same sense amplifier can be used for the logical operations. For example, two word lines on one digit line and one word line on another digit line can be substantially concurrently activated to perform a particular logical operation. These three word lines are respectively coupled to memory cells configured to store either operands of operation or a reference data value for the particular logical.

公开(公告)号：US11967361B2

公开(公告)日：2024-04-23

申请号：US17589417

申请日：2022-01-31

Applicant: Micron Technology, Inc.

Inventor： Kyle B. Wheeler ,  Troy A. Manning ,  Richard C. Murphy

IPC: G11C11/408 ,  G11C7/06 ,  G11C7/10 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4096

CPC classification number: G11C11/4091 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/1012 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4093 ,  G11C11/4096

Abstract: One example of the present disclosure includes performing a comparison operation in memory using a logical representation of a first value stored in a first portion of a number of memory cells coupled to a sense line of a memory array and a logical representation of a second value stored in a second portion of the number of memory cells coupled to the sense line of the memory array. The comparison operation compares the first value to the second value, and the method can include storing a logical representation of a result of the comparison operation in a third portion of the number of memory cells coupled to the sense line of the memory array.

公开(公告)号：US11727963B2

公开(公告)日：2023-08-15

申请号：US17693994

申请日：2022-03-14

Applicant: Micron Technology, Inc.

Inventor： Troy A. Manning

IPC: G11C7/06 ,  G06F12/00 ,  G11C7/10 ,  G11C15/00 ,  G11C11/4096 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4094

CPC classification number: G11C7/065 ,  G06F12/00 ,  G11C7/1006 ,  G11C7/1051 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4096 ,  G11C15/00 ,  G11C11/4094

Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry is configured to perform a logical operation using a data value stored in a first memory cell coupled to a sense line as a first input and a data value stored in a second memory cell coupled to the sense line as a second input. The sensing circuitry is configured to perform the logical operation without transferring data via a sense line address access.

公开(公告)号：US20230079504A1

公开(公告)日：2023-03-16

申请号：US17981696

申请日：2022-11-07

Applicant: Micron Technology, Inc.

Inventor： Troy A. Manning

IPC: G11C7/22 ,  G06F12/00 ,  G11C7/06 ,  G11C11/4074 ,  G11C11/4091 ,  G06F3/06 ,  G06F7/523 ,  H03K19/1776 ,  H03K19/00 ,  G11C7/10

Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry comprising a primary latch coupled to a sense line of the array. The sensing circuitry can be configured to perform a first operation phase of a logical operation by sensing a memory cell coupled to the sense line, perform a number of intermediate operation phases of the logical operation by sensing a respective number of different memory cells coupled to the sense line, and accumulate a result of the first operation phase and the number of intermediate operation phases in a secondary latch coupled to the primary latch without performing a sense line address access.

公开(公告)号：US20220335987A1

公开(公告)日：2022-10-20

申请号：US17855212

申请日：2022-06-30

Applicant: Micron Technology, Inc.

Inventor： Timothy P. Finkbeiner ,  Troy A. Manning ,  Troy D. Larsen ,  Glen E. Hush

IPC: G11C7/06 ,  G11C7/10

Abstract: Methods and devices related to transferring data between DRAM and SRAM. One method includes activating a first portion of a dynamic random access memory (DRAM), reading data from the first portion of the DRAM, latching the data from the first portion of the DRAM in one or more sense amplifiers, and writing the data from the one or more sense amplifiers to a first portion of a static random access memory (SRAM).