公开(公告)号：US20200177172A1

公开(公告)日：2020-06-04

申请号：US16784002

申请日：2020-02-06

Applicant: Micron Technology, Inc.

Inventor： Yasuo Satoh

IPC: H03K5/156 ,  H03K5/19 ,  H03K3/017 ,  H03L7/18

Abstract: Several embodiments of electrical circuit devices and systems with a duty cycle correction apparatus that includes a duty cycle adjustment circuit that is configured to adjust a duty cycle of the input clock signal based on an averaged code value. The duty cycle correction apparatus includes a duty cycle detector circuit that receives first and second clock signals from a clock distribution network. The duty cycle detector is configured to output a duty cycle status signal that indicates whether the first clock signal is above or below a 50% duty cycle based on a comparison of the first clock signal to the second clock signal. The duty cycle correction apparatus also includes a counter logic circuit configured to determine the average code value, and the counter logic circuit automatically cancels an offset of the duty cycle detector when determining the averaged code value.

公开(公告)号：US20200153443A1

公开(公告)日：2020-05-14

申请号：US16746352

申请日：2020-01-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yasuo Satoh

IPC: H03L7/099 ,  H03L7/081 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4093 ,  H03L7/089 ,  H03L7/10

Abstract: Apparatuses and methods are disclosed for detecting a loop count in a delay-locked loop that uses a divide clock in a measure initialization process. An example apparatus includes a divider configured to receive a signal and produce a first divided signal and a second divided signal that is complementary to the first divided signal, a first circuit configured to count the first divided signal during a first enabled period and produce a first count value, a second circuit configured to count the second divided signal during a second enabled period and produce a second count value, and an adder configured to produce a third count value responsive to the first and second count values.

公开(公告)号：US10529390B1

公开(公告)日：2020-01-07

申请号：US16205450

申请日：2018-11-30

Applicant: Micron Technology, Inc.

Inventor： Yasuo Satoh ,  Yuan He

IPC: G11C7/10 ,  G06F3/06

Abstract: A memory system includes an external calibration device that has a predetermined impedance and a first memory device with a first pad for selective connection to the external calibration device. The first memory device also includes an internal calibration device having an impedance that is programmable and a second pad connected to the internal calibration device. The system further includes a second memory device having a third pad for selective connection to the second pad of the first memory device. A processing device is operatively coupled to the first memory device and the second memory device. The processing device programs the impedance of the internal calibration device of the first memory device based on the external calibration device, and programs an impedance of a termination component in the second memory device based on the impedance of the internal calibration device of the first memory device.

公开(公告)号：US10461759B2

公开(公告)日：2019-10-29

申请号：US16136046

申请日：2018-09-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yasuo Satoh

IPC: H03L7/193 ,  H03K5/13 ,  H03L7/08 ,  H03K21/10 ,  H03L7/099

Abstract: Disclosed herein is an apparatus that includes a variable clock divider configured to divide a first clock signal to generate a second clock signal, a delay circuit configured to delay the second clock signal to generate a third clock signal, and a phase detector configured to compare phases of the second and third clock signals. The variable clock divider has a division ratio that is variable based, at least in part, on a delay amount of the delay circuit.

公开(公告)号：US10438648B2

公开(公告)日：2019-10-08

申请号：US15868232

申请日：2018-01-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yasuo Satoh ,  Tyler J. Gomm

IPC: G11C11/4076 ,  H03K3/017 ,  H03K23/00 ,  H03M7/16 ,  G11C29/02 ,  H03K19/21

Abstract: Apparatuses and methods for maintaining a duty cycle error counter. An example apparatus may a duty cycle detect circuit configured to receive a clock signal and to detect a duty cycle error of the clock signal. The duty cycle detect error includes a counter configured to store a count value indicating the duty cycle error using Gray code. The counter is adjusted in response to detection of non-zero duty cycle error, and the counter is configured to convert the count value from Gray code to binary code as a binary count value. The duty cycle detect circuit is further configured to provide a duty cycle error signal based on the binary count value. The example apparatus further comprising a duty cycle correction circuit configured to adjust a duty cycle of the clock signal based on the duty cycle error signal.

公开(公告)号：US20190268009A1

公开(公告)日：2019-08-29

申请号：US16406480

申请日：2019-05-08

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yasuo Satoh

IPC: H03L7/14 ,  H04L7/04 ,  H03L7/087 ,  H03L7/18 ,  H04L5/26

Abstract: Apparatuses and methods for providing frequency divided clocks are described. An example apparatus includes a first circuit configured to provide a first intermediate clock responsive, at least in part, to a first input clock, the first intermediate clock being lower in frequency than the first input clock and further includes a second circuit configured to provide a second intermediate clock and a third intermediate clock responsive, at least in part, to a second input clock, the second intermediate clock being complementary to the third intermediate clock and lower in frequency than the second input clock. The apparatus further includes a third circuit configured to select and provide as an output clock one of the second and third intermediate clocks responsive, at least in part, to the first and second intermediate clocks.

公开(公告)号：US20190207592A1

公开(公告)日：2019-07-04

申请号：US16294640

申请日：2019-03-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tyler J. Gomm ,  Yasuo Satoh

IPC: H03K3/037

CPC classification number: H03K3/0372 ,  G11C7/106 ,  G11C7/222 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4085 ,  G11C11/4087 ,  G11C11/4093 ,  H03K3/017 ,  H03K19/20

Abstract: Methods and apparatuses of a two-phase flip-flop with symmetrical rise and fall times are disclosed herein. An example apparatus may include a clock generator circuit including a two-phase flip-flop circuit configured to provide an output signal. The two-phase flip-flop circuit includes a two-phase flip-flop and a driver circuit. The two-phase flip-flop is configured to provide a first driver control signal and a second driver control signal responsive to a clock signal. The first driver control signal and the second driver control signal are complementary. The driver circuit is configured to provide the output signal responsive to the first driver control signal and the second driver control signal.

公开(公告)号：US10333532B2

公开(公告)日：2019-06-25

申请号：US15697773

申请日：2017-09-07

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yasuo Satoh

IPC: H03L7/099 ,  H03L7/10 ,  H03L7/081 ,  H03L7/089

Abstract: Apparatuses and methods are disclosed for detecting a loop count in a delay-locked loop that uses a divide clock in a measure initialization process. An example apparatus includes a divider configured to receive a signal and produce a first divided signal and a second divided signal that is complementary to the first divided signal, a first circuit configured to count the first divided signal during a first enabled period and produce a first count value, a second circuit configured to count the second divided signal during a second enabled period and produce a second count value, and an adder configured to produce a third count value responsive to the first and second count values.

公开(公告)号：US20190181847A1

公开(公告)日：2019-06-13

申请号：US15839531

申请日：2017-12-12

Applicant: Micron Technology, Inc.

Inventor： Yasuo Satoh ,  Kazutaka Miyano

IPC: H03K5/156 ,  G11C7/22 ,  H03K3/017 ,  H03L7/081 ,  G11C7/12

CPC classification number: H03K5/1565 ,  G11C7/1018 ,  G11C7/12 ,  G11C7/222 ,  G11C11/4076 ,  H03K3/017 ,  H03L7/0812

Abstract: Apparatuses and methods for data transmission offset values in burst transmissions. An example apparatus may include offset logic configured to provide offset values associated with a receiver circuit of a memory device coupled to a signal line. The offset values are based on individual transition threshold voltages biases of sample circuits of the receiver circuit. The example apparatus may further include an input/output (I/O) circuit comprising a driver circuit. The driver circuit configured to receive a logic signal and the offset values and to provide an output signal to the signal line based on the logic signal and to adjust voltages of the output signal based on the offset values.

公开(公告)号：US20190097613A1

公开(公告)日：2019-03-28

申请号：US15717610

申请日：2017-09-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tyler J. Gomm ,  Yasuo Satoh

IPC: H03K3/037

Abstract: Methods and apparatuses of a two-phase flip-flop with symmetrical rise and fall times are disclosed herein. An example apparatus may include a clock generator circuit including a two-phase flip-flop circuit configured to provide an output signal. The two-phase flip-flop circuit includes a two-phase flip-flop and a driver circuit. The two-phase flip-flop is configured to provide a first driver control signal and a second driver control signal responsive to a clock signal. The first driver control signal and the second driver control signal are complementary. The driver circuit is configured to provide the output signal responsive to the first driver control signal and the second driver control signal.