公开(公告)号：US08879681B2

公开(公告)日：2014-11-04

申请号：US13849414

申请日：2013-03-22

Applicant: NVIDIA Corporation

Inventor： William J. Dally ,  Stephen G. Tell

IPC: H04L7/00 ,  H04L7/033

CPC classification number: H04L7/033 ,  H04L7/0012 ,  H04L7/005

Abstract: A system and method are provided for determining a time for safely sampling a signal of a dock domain. In one embodiment, a frequency estimate of a first clock domain is calculated utilizing a frequency estimator. Additionally, a time during which a signal from the first clock domain is unchanging is determined such that the signal is capable of being safely sampled by a second clock domain, using the frequency estimate. In another embodiment, a frequency estimate of a first dock domain is calculated utilizing a frequency estimator. Further, a phase estimate of the first clock domain is calculated based on the frequency estimate, utilizing a phase estimator. Moreover, a time during which a signal from the first clock domain is unchanging is determined such that the signal is capable of being safely sampled by a second clock domain, using the phase estimate.

Abstract translation: 提供了一种系统和方法，用于确定用于对码区域的信号进行安全采样的时间。 在一个实施例中，使用频率估计器来计算第一时钟域的频率估计。 此外，确定来自第一时钟域的信号不变的时间，使得信号能够使用频率估计被第二时钟域安全地采样。 在另一实施例中，使用频率估计器来计算第一对接域的频率估计。 此外，利用相位估计器，基于频率估计来计算第一时钟域的相位估计。 此外，确定来自第一时钟域的信号不变的时间，使得信号能够使用相位估计被第二时钟域安全地采样。

公开(公告)号：US20140312868A1

公开(公告)日：2014-10-23

申请号：US13868975

申请日：2013-04-23

Applicant: NVIDIA CORPORATION

Inventor： William J. Dally

IPC: H02M3/158

CPC classification number: H02M3/1588 ,  Y02B70/1466

Abstract: A system and method are provided for controlling a multi-phase switching regulator including a first phase and a second phase, where the first phase includes a first modified buck regulator circuit and the second phase includes a second modified buck regulator circuit. The first phase and the second phase are activated. The first phase is operated in a soft-switching mode to provide current to a load for a first portion of an operating cycle and the second phase is operated in a soft-switching mode to provide current to the load for a second portion of the operating cycle.

Abstract translation: 提供了一种系统和方法，用于控制包括第一相和第二相的多相开关调节器，其中第一相包括第一修正降压调节器电路，第二相包括第二修正降压调节器电路。 第一阶段和第二阶段被激活。 第一阶段以软切换模式操作，以向操作周期的第一部分的负载提供电流，并且第二相以软切换模式操作，以向操作中的第二部分的负载提供电流 周期。

公开(公告)号：US08841953B2

公开(公告)日：2014-09-23

申请号：US13775063

申请日：2013-02-22

Applicant: NVIDIA Corporation

Inventor： William J. Dally

IPC: H03K3/00 ,  H03K3/012

CPC classification number: H03K3/012 ,  H03K3/356121

Abstract: A double-edge-triggered flip-flop circuit and a method for operating the double-edge-trigger flip-flop circuit are provided. Sub-circuits of a flip-flop circuit are coupled to a ground supply and decoupled the sub-circuits from a power supply when a clock signal is asserted. The sub-circuits generate trigger signals including a first pair of signals and a second pair of signals. The first pair of signals is evaluated, levels of the second pair of signals are maintained when the clock signal is asserted, and an output signal is transitioned to equal an input signal based on the trigger signals when the clock signal is asserted.

Abstract translation: 提供双边沿触发触发器电路和用于操作双边沿触发器触发器电路的方法。 当时钟信号被断言时，触发器电路的子电路耦合到接地电源并将子电路与电源解耦。 子电路产生包括第一对信号和第二对信号的触发信号。 评估第一对信号，当时钟信号被断言时，第二对信号的电平被维持，并且当时钟信号被断言时，输出信号基于触发信号转换到等于输入信号。

公开(公告)号：US20140268976A1

公开(公告)日：2014-09-18

申请号：US13844570

申请日：2013-03-15

Applicant: NVIDIA CORPORATION

Inventor： William J. Dally ,  Brucek Kurdo Khailany ,  Thomas Hastings Greer, III ,  John W. Poulton

IPC: G11C5/06

CPC classification number: G11C7/1057 ,  G11C7/1069 ,  H01L2224/0401 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/15192 ,  H01L2924/15311

Abstract: A system is provided for transmitting signals. The system comprises a first processing unit, a memory subsystem, and a package. The first processing unit is configured to include a first ground-referenced single-ended signaling (GRS) interface circuit. The memory subsystem is configured to include a second GRS interface circuit. The package is configured to include one or more electrical traces that couple the first GRS interface to the second GRS interface, where the first GRS interface circuit and the second GRS interface circuit are each configured to transmit a pulse along one trace of the one or more electrical traces by discharging a capacitor between the one trace and a ground network.

Abstract translation: 提供用于发送信号的系统。 该系统包括第一处理单元，存储器子系统和封装。 第一处理单元被配置为包括第一接地参考单端信令（GRS）接口电路。 存储器子系统被配置为包括第二GRS接口电路。 所述包装被配置为包括将所述第一GRS接口耦合到所述第二GRS接口的一个或多个电迹线，其中所述第一GRS接口电路和所述第二GRS接口电路各自被配置为沿着所述一个或多个 通过在一个迹线和地面网络之间放电电容器的电迹线。

公开(公告)号：US20140210429A1

公开(公告)日：2014-07-31

申请号：US13752289

申请日：2013-01-28

Applicant: NVIDIA CORPORATION

Inventor： William J. Dally

IPC: G05F3/02

CPC classification number: G05F3/02 ,  H02M3/1582 ,  H02M3/1588 ,  H02M2001/0016 ,  H02M2001/0032 ,  H02M2003/1586 ,  Y02B70/1425 ,  Y02B70/1466 ,  Y02B70/16

Abstract: A system and method are provided for regulating a voltage level at a load. The method configures a current control mechanism to generate a current through a first inductor and a second inductor that are coupled in series and configures a voltage control mechanism to provide a portion of the current to regulate the voltage level. The second inductor isolates the load from a parasitic capacitance of the current control mechanism. An electric power conversion device for regulating the voltage level at the load comprises the current control mechanism that is coupled to an electric power source and configured to generate a current through the first inductor and the second inductor that are coupled in series and the voltage control mechanism that is coupled to the second inductor and configured to provide a portion of the current to regulate the voltage level.

Abstract translation: 提供了一种用于调节负载电压电平的系统和方法。 该方法配置电流控制机制以通过串联耦合的第一电感器和第二电感器产生电流，并配置电压控制机构以提供电流的一部分来调节电压电平。 第二个电感将负载与电流控制机构的寄生电容隔离开来。 用于调节负载电压电平的电力转换装置包括电流控制机构，该电流控制机构耦合到电源并被配置为产生通过串联耦合的第一电感器和第二电感器的电流，以及电压控制机构 其耦合到第二电感器并且被配置为提供电流的一部分以调节电压电平。

公开(公告)号：US20140149780A1

公开(公告)日：2014-05-29

申请号：US13688170

申请日：2012-11-28

Applicant: NVIDIA CORPORATION

Inventor： William J. Dally ,  Stephen G. Tell

IPC: G06F1/12

CPC classification number: G06F1/12

Abstract: A method and a system are provided for speculative periodic synchronization. A phase value representing a measured phase of the second clock signal relative to the first clock signal measured at least one cycle earlier is received. A period value representing a period of the second clock signal relative to the first clock signal measured at least one cycle earlier is also received. A reduced timing margin is determined based on the phase value and the period value. A speculatively synchronized output signal is generated based on the reduced timing margin.

Abstract translation: 提供了一种用于推测周期性同步的方法和系统。 接收表示相对于在至少一个周期测量的第一时钟信号的第二时钟信号的测量相位的相位值。 还接收表示相对于先前测量的至少一个周期的第一时钟信号的第二时钟信号的周期的周期值。 基于相位值和周期值确定缩短的定时裕度。 基于减小的时序余量产生推测同步的输出信号。

公开(公告)号：US20140139276A1

公开(公告)日：2014-05-22

申请号：US13688175

申请日：2012-11-28

Applicant: NVIDIA CORPORATION

Inventor： William J. Dally

IPC: H03L7/00

CPC classification number: H03L7/00 ,  G06F1/10 ,  H03K5/00 ,  H03K2005/00104 ,  H03K2005/00241

Abstract: A method and a system are provided for clock phase detection. A first set of delayed versions of a first clock signal is generated and a second set of delayed versions of a second clock signal is generated. The second set of delayed versions of the second clock signal is sampled using the first set of delayed versions of the first clock signal to produce an array of clock samples in a domain corresponding to the first clock signal. At least one edge indication is located within the array of clock samples.

Abstract translation: 提供了一种用于时钟相位检测的方法和系统。 生成第一时钟信号的第一组延迟版本，并且产生第二组第二时钟信号的延迟版本。 使用第一时钟信号的第一组延迟版本对第二时钟信号的第二组延迟版本进行采样，以产生与第一时钟信号对应的域中的时钟采样阵列。 至少一个边缘指示位于时钟采样阵列内。

公开(公告)号：US20140044159A1

公开(公告)日：2014-02-13

申请号：US14055823

申请日：2013-10-16

Applicant: NVIDIA Corporation

Inventor： John W. Poulton ,  Thomas Hastings Greer, III ,  William J. Dally

IPC: H03K17/16 ,  H04B1/04

CPC classification number: H03K17/16 ,  H04B1/04 ,  H04L25/0274 ,  H04L25/028 ,  H04L25/0292 ,  H04L25/03878

Abstract: One embodiment of the present invention sets forth a mechanism for transmitting and receiving ground-referenced single-ended signals. A transmitter combines a direct current (DC) to DC converter including a flying capacitor with a 2:1 clocked multiplexer to drive a single-ended signaling line. The transmitter drives a pair of voltages that are symmetric about the ground power supply level. Signaling currents are returned to the ground plane to minimize the generation of noise that is a source of crosstalk between different signaling lines. Noise introduced through the power supply is correlated with the switching rate of the data and may be reduced using an equalizer circuit.

Abstract translation: 本发明的一个实施例提出了用于发送和接收地参考单端信号的机制。 发射机将直流（DC）到DC转换器组合，其中包括具有2：1时钟多路复用器的飞跨电容器，以驱动单端信号线。 发射机驱动一对对地面电源电平对称的电压。 信号电流返回到接地平面，以最小化作为不同信号线之间的串扰源的噪声的产生。 通过电源引入的噪声与数据的切换速率相关，并且可以使用均衡器电路来减小。

公开(公告)号：US20130216013A1

公开(公告)日：2013-08-22

申请号：US13849414

申请日：2013-03-22

Applicant: NVIDIA CORPORATION

Inventor： William J. Dally ,  Stephen G. Tell

IPC: H04L7/033

CPC classification number: H04L7/033 ,  H04L7/0012 ,  H04L7/005

Abstract: A system and method are provided for determining a time for safely sampling a signal of a dock domain. In one embodiment, a frequency estimate of a first clock domain is calculated utilizing a frequency estimator. Additionally, a time during which a signal from the first clock domain is unchanging is determined such that the signal is capable of being safely sampled by a second clock domain, using the frequency estimate. In another embodiment, a frequency estimate of a first dock domain is calculated utilizing a frequency estimator. Further, a phase estimate of the first clock domain is calculated based on the frequency estimate, utilizing a phase estimator. Moreover, a time during which a signal from the first clock domain is unchanging is determined such that the signal is capable of being safely sampled by a second clock domain, using the phase estimate.

Abstract translation: 提供了一种系统和方法，用于确定用于对码区域的信号进行安全采样的时间。 在一个实施例中，使用频率估计器来计算第一时钟域的频率估计。 此外，确定来自第一时钟域的信号不变的时间，使得信号能够使用频率估计由第二时钟域安全地采样。 在另一实施例中，使用频率估计器来计算第一对接域的频率估计。 此外，利用相位估计器，基于频率估计来计算第一时钟域的相位估计。 此外，确定来自第一时钟域的信号不变的时间，使得信号能够使用相位估计被第二时钟域安全地采样。

公开(公告)号：US11847550B2

公开(公告)日：2023-12-19

申请号：US17111875

申请日：2020-12-04

Applicant: NVIDIA Corporation

Inventor： William J. Dally ,  Angshuman Parashar ,  Joel Springer Emer ,  Stephen William Keckler ,  Larry Robert Dennison

IPC: G06N3/04 ,  G06N3/042 ,  G06F17/11 ,  G06F9/30 ,  G06F9/38 ,  G06N3/082 ,  G06N3/063 ,  G06N3/045 ,  G06N3/048 ,  G06F7/544 ,  G06F9/355 ,  G06F17/16 ,  G06F9/28

CPC classification number: G06N3/042 ,  G06F7/5443 ,  G06F9/3001 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30036 ,  G06F9/3851 ,  G06F9/3887 ,  G06F17/11 ,  G06N3/045 ,  G06N3/048 ,  G06N3/063 ,  G06N3/082 ,  G06F9/28 ,  G06F9/3555 ,  G06F17/16 ,  G06F2207/4824

Abstract: A method, computer program product, and system perform computations using a processor. A first instruction including a first index vector operand and a second index vector operand is received and the first index vector operand is decoded to produce first coordinate sets for a first array, each first coordinate set including at least a first coordinate and a second coordinate of a position of a non-zero element in the first array. The second index vector operand is decoded to produce second coordinate sets for a second array, each second coordinate set including at least a third coordinate and a fourth coordinate of a position of a non-zero element in the second array. The first coordinate sets are summed with the second coordinate sets to produce output coordinate sets and the output coordinate sets are converted into a set of linear indices.