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    PROTOCOL FOR MEMORY POWER-MODE CONTROL
    52.
    发明申请
    PROTOCOL FOR MEMORY POWER-MODE CONTROL 有权
    用于存储器功率模式控制的协议

    公开(公告)号：US20150103610A1

    公开(公告)日：2015-04-16

    申请号：US14573323

    申请日：2014-12-17

    Applicant: Rambus Inc.

    Inventor： Wayne F. Ellis ,  Wayne S. Richardson ,  Akash Bansal ,  Frederick A. Ware ,  Lawrence Lai ,  Kishore Ven Kasamsetty

    IPC: G11C11/406 ,  G11C11/4074

    CPC classification number: G11C11/40615 ,  G06F1/3234 ,  G11C7/02 ,  G11C7/20 ,  G11C11/4072 ,  G11C11/4074 ,  G11C29/022 ,  G11C29/028

    Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.

    Abstract translation: 在一个实施例中，存储器设备包括存储器核心和用于接收命令和数据的输入接收器。 存储器装置还包括寄存器，用于存储指示输入接收器的子集是否响应于控制信号掉电的值。 存储器控制器将命令和数据发送到存储器件。 存储器控制器还发送该值以指示存储器件的输入接收器的子集是否响应于控制信号掉电。 此外，响应于自我新命令，存储装置延迟进入自刷新操作，直到接收到接收到自刷新命令后接收的控制信号为止。

    Memory Controller For Micro-Threaded Memory Operations
    53.
    发明申请
    Memory Controller For Micro-Threaded Memory Operations 有权
    用于微线程存储器操作的存储器控​​制器

    公开(公告)号：US20140344546A1

    公开(公告)日：2014-11-20

    申请号：US14449610

    申请日：2014-08-01

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Craig E. Hampel ,  Wayne S. Richardson ,  Chad A. Bellows ,  Lawrence Lai

    IPC: G06F3/06 ,  G11C7/10

    CPC classification number: G06F3/0659 ,  G06F3/0613 ,  G06F3/0673 ,  G11C7/1006 ,  G11C7/1042 ,  G11C7/22 ,  G11C8/06 ,  G11C11/4076 ,  G11C11/4097

    Abstract: A micro-threaded memory device. A plurality of storage banks are provided, each including a plurality of rows of storage cells and having an access restriction in that at least a minimum access time interval must transpire between successive accesses to a given row of the storage cells. Transfer control circuitry is provided to transfer a first amount of data between the plurality of storage banks and an external signal path in response to a first memory access request, the first amount of data being less than a product of the external signal path bandwidth and the minimum access time interval.

    Abstract translation: 微线程存储器件。 提供了多个存储体，每个存储体包括多行存储单元并且具有访问限制，因为至少最小访问时间间隔必须在对存储单元的给定行的连续访问之间发生。 提供传送控制电路以响应于第一存储器访问请求在多个存储体和外部信号路径之间传送第一数据量，第一数据量小于外部信号路径带宽和 最小访问时间间隔。

    DATA WRITE FROM PRE-PROGRAMMED REGISTER
    56.
    发明申请
    DATA WRITE FROM PRE-PROGRAMMED REGISTER 有权

    公开(公告)号：US20220206936A1

    公开(公告)日：2022-06-30

    申请号：US17540437

    申请日：2021-12-02

    Applicant: Rambus Inc.

    Inventor： Thomas J. Sheffler ,  Lawrence Lai ,  Liang Peng ,  Bohuslav Rychlik

    IPC: G06F12/02 ,  G11C7/22 ,  G11C8/10 ,  G11C7/10

    Abstract: A memory access command, column address and plurality of write data values are received within an integrated-circuit memory chip via external signaling links. In response to the memory access command, the integrated-circuit memory chip (i) decodes the column address to select address-specified sense amplifiers from among a plurality of sense amplifiers that constitute a sense amplifier bank, (ii) reads first data, constituted by a plurality of read data values, out of the address-specified sense amplifiers, and (iii) overwrites the first data within the address-specified sense amplifiers with second data constituted by one or more of the write data values and by one or more of the read data values.

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