公开(公告)号：US11599483B2

公开(公告)日：2023-03-07

申请号：US17581659

申请日：2022-01-21

Applicant: Rambus Inc.

Inventor： Liji Gopalakrishnan

IPC: G06F13/16 ,  G11C11/4093 ,  G11C11/4096

Abstract: A memory system includes a dynamic random access memory (DRAM) device, a second memory device, and a memory controller circuit. The memory controller circuit is coupled to the DRAM device by a first data channel configured to transfer first data between the memory controller circuit and the DRAM device on behalf of a host, and is also coupled to the DRAM device by a second data channel configured to transfer second data between the memory controller circuit and the DRAM device on behalf of the second memory device while the first data is being transferred across the first data bus.

公开(公告)号：US11372795B2

公开(公告)日：2022-06-28

申请号：US16942970

申请日：2020-07-30

Applicant: Rambus Inc.

Inventor： Liji Gopalakrishnan ,  Ian Shaeffer ,  Yi Lu

IPC: G06F13/40 ,  G11C7/10 ,  G11C11/4093 ,  G11C11/4094 ,  G11C5/04 ,  G06F13/16 ,  G11C11/4096

Abstract: A memory device or module selects between alternative command ports. Memory systems with memory modules incorporating such memory devices support point-to-point connectivity and efficient interconnect usage for different numbers of modules. The memory devices and modules can be of programmable data widths. Devices on the same module can be configured select different command ports to facilitate memory threading. Modules can likewise be configured to select different command ports for the same purpose.

公开(公告)号：US11226909B2

公开(公告)日：2022-01-18

申请号：US16546176

申请日：2019-08-20

Applicant: Rambus Inc.

Inventor： Liji Gopalakrishnan ,  Frederick A. Ware ,  Brent S. Haukness

IPC: G06F3/00 ,  G06F13/16 ,  G06F3/06

Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, an integrated circuit (IC) memory device is disclosed. The memory device includes an array of storage cells and command interface circuitry to receive an internal transfer command. In response to the internal transfer command, transfer logic reads data from a first portion of the array of storage cells, transfers the data as on-chip transfer data, and writes the on-chip transfer data to a second portion of the array of storage cells. In response to the command interface circuitry receiving an interrupt command, the transfer logic pauses the internal transfer operation, and carries out an unrelated memory access operation involving at least the first portion of the array of storage cells or the second portion of the array of storage cells.

公开(公告)号：US11114150B2

公开(公告)日：2021-09-07

申请号：US16838646

申请日：2020-04-02

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang ,  John Eric Linstadt ,  Liji Gopalakrishnan

IPC: G11C11/408 ,  G11C11/4094 ,  G11C11/4091 ,  G06F13/42

Abstract: A dynamic random access memory (DRAM) component (e.g., module or integrated circuit) can be configured to have multiple rows in the same bank open concurrently. The controller of the component divides the address space of the banks into segments based on row address ranges. These row address ranges do not necessarily correspond to row address ranges of the bank's subarrays (a.k.a. memory array tiles—MATs). When a command is sent to open a row, the controller marks a plurality of the segments as blocked. The controller thereby tracks address ranges in a bank where it will not open a second row unless and until the first row is closed. The memory component may store information about which, and how many, segments should be blocked in response to opening a row. This information may be read by the controller during initialization.

公开(公告)号：US20200349997A1

公开(公告)日：2020-11-05

申请号：US16865928

申请日：2020-05-04

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Lei Luo ,  Liji Gopalakrishnan

IPC: G11C11/4076 ,  G11C11/4096 ,  G11C7/10 ,  G11C7/20 ,  G11C7/22 ,  G11C11/4072 ,  G11C11/4074 ,  G06F1/3237 ,  G06F1/04 ,  G06F1/3234 ,  G06F1/08 ,  G11C11/408

Abstract: An integrated circuit includes a physical layer interface having a control timing domain and a data timing domain, and circuits that enable the control timing domain during a change in power conservation mode in response to a first event, and that enable the data timing domain in response to a second event. The control timing domain can include interface circuits coupled to a command and address path, and the data timing domain can include interface circuits coupled to a data path.

公开(公告)号：US20200065268A1

公开(公告)日：2020-02-27

申请号：US16546176

申请日：2019-08-20

Applicant: Rambus Inc.

Inventor： Liji Gopalakrishnan ,  Frederick A. Ware ,  Brent S. Haukness

IPC: G06F13/16 ,  G06F3/06

Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, an integrated circuit (IC) memory device is disclosed. The memory device includes an array of storage cells and command interface circuitry to receive an internal transfer command. In response to the internal transfer command, transfer logic reads data from a first portion of the array of storage cells, transfers the data as on-chip transfer data, and writes the on-chip transfer data to a second portion of the array of storage cells. In response to the command interface circuitry receiving an interrupt command, the transfer logic pauses the internal transfer operation, and carries out an unrelated memory access operation involving at least the first portion of the array of storage cells or the second portion of the array of storage cells.

公开(公告)号：US10209922B2

公开(公告)日：2019-02-19

申请号：US14806788

申请日：2015-07-23

Applicant: Rambus Inc.

Inventor： Liji Gopalakrishnan ,  Vlad Fruchter ,  Lawrence Lai ,  Pradeep Batra ,  Steven C. Woo ,  Wayne Frederick Ellis

IPC: G06F3/06 ,  G06F13/16 ,  G06F12/06 ,  G11C7/10

Abstract: A memory space of a module connected to a memory controller via a memory interface may be used as a command buffer. Commands received by the module via the command buffer are executed by the module. The memory controller may write to the command buffer out-of-order. The memory controller may delay or eliminate writes to the command buffer. Tags associated with commands are used to specify the order commands are executed. A status buffer in the memory space of the module is used to communicate whether commands have been received or executed. Information received via the status buffer can be used as a basis for a determination to re-send commands to the command buffer.

公开(公告)号：US20190043551A1

公开(公告)日：2019-02-07

申请号：US16032633

申请日：2018-07-11

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Lei Luo ,  Liji Gopalakrishnan

IPC: G11C11/4076 ,  G11C11/4096 ,  G11C7/22 ,  G06F1/04 ,  G11C7/10 ,  G06F1/32 ,  G11C11/408 ,  G11C11/4072 ,  G11C11/4074 ,  G06F1/08 ,  G11C7/20

CPC classification number: G11C11/4076 ,  G06F1/04 ,  G06F1/08 ,  G06F1/3234 ,  G06F1/3237 ,  G11C7/1072 ,  G11C7/20 ,  G11C7/22 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/4087 ,  G11C11/4096 ,  Y02D10/128 ,  Y02D50/20

Abstract: An integrated circuit includes a physical layer interface having a control timing domain and a data timing domain, and circuits that enable the control timing domain during a change in power conservation mode in response to a first event, and that enable the data timing domain in response to a second event. The control timing domain can include interface circuits coupled to a command and address path, and the data timing domain can include interface circuits coupled to a data path.

公开(公告)号：US10089256B2

公开(公告)日：2018-10-02

申请号：US15616785

申请日：2017-06-07

Applicant: Rambus Inc.

Inventor： Pravin Kumar Venkatesan ,  Liji Gopalakrishnan ,  Kashinath Prabhu ,  Makarand Shirasgaonkar

IPC: G06F13/16

Abstract: A transmitter is coupled to a command and address (CA) bus. The transmitter is configurable with dual-mode support to send commands over the CA bus in a first swing mode and a second swing mode. The transmitter is configurable to send a first command over the CA bus via the pins while in the first swing mode, initiate calibration of the master device to send commands over the CA bus in the second swing mode, and to send a second command over the CA bus via the pins while in the second swing mode.

公开(公告)号：US09287003B2

公开(公告)日：2016-03-15

申请号：US14325140

申请日：2014-07-07

Applicant: RAMBUS INC.

Inventor： Liji Gopalakrishnan ,  Mahabaleshwara Mahabaleshwara

IPC: G11C7/00 ,  G11C29/02 ,  G06F11/10 ,  G06F11/14

CPC classification number: G11C29/023 ,  G06F11/1076 ,  G06F11/14 ,  G11C29/021 ,  G11C29/022 ,  G11C29/028

Abstract: A memory controller includes logic to determine corresponding reference voltage values and delay values for one or more memory devices. The memory controller includes a command-address (CA) interface to send a command to a memory device to set a reference voltage value of the memory device to a test value, a data interface to write a data pattern to the memory device and read the data pattern from the memory device, and test reference voltage logic to perform a density check on at least a portion of the data pattern read from the memory device and determine whether the test value is a potential reference voltage value based on the density check. An operational reference voltage value selected from one or more potential reference voltage values may be used to determine a delay value.

Abstract translation: 存储器控制器包括用于确定一个或多个存储器件的相应参考电压值和延迟值的逻辑。 存储器控制器包括命令地址（CA）接口，用于向存储器件发送命令以将存储器件的参考电压值设置为测试值，数据接口将数据模式写入存储器件并读取 来自存储器件的数据模式，以及测试参考电压逻辑，以对从存储器件读取的数据模式的至少一部分执行密度检查，并且基于密度检查确定测试值是否是潜在的参考电压值。 可以使用从一个或多个潜在参考电压值中选择的操作参考电压值来确定延迟值。