公开(公告)号：US10325981B2

公开(公告)日：2019-06-18

申请号：US15909989

申请日：2018-03-01

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Tsung-Yi Huang

IPC: H01L29/76 ,  H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L29/66

Abstract: A high-side device includes: a substrate, an epitaxial layer, a high voltage well, a body region, a gate, a source, a drain, two buried regions. A PN junction is formed between the body region and the high voltage well, wherein the PN junction is perpendicular to a channel direction. One buried region is formed in the epitaxial layer and has a first conductive type, wherein an inner side boundary thereof is located between the drain and the PN junction. The other buried region is formed in the substrate and in the epitaxial layer and has a second conductive type, wherein an inner side boundary thereof is located between the drain and the PN junction. The impurity concentration of the second buried region is sufficient to prevent the high voltage well between the PN junction and the drain from being completely depleted when the high-side power device is ON.

公开(公告)号：US20190131390A1

公开(公告)日：2019-05-02

申请号：US16130921

申请日：2018-09-13

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Tsung-Yi Huang ,  Chu-Feng Chen

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L29/66

Abstract: A high voltage MOS device includes: a well, a drift region, a gate, a source, a drain, and plural buried columns. A part of the gate is stacked on a part of the well, and another part of the gate is stacked on a part of the drift region. The source connects the well in a lateral direction. The drain connects the drift region in the lateral direction. The drain and the source are separated by the well and the drift region, and the drain and the source are located at different sides of the gate. The plural buried columns are formed beneath the top surface by a predetermined distance, and each buried column does not connect the top surface. At least a part of every buried column is surrounded by the drift region, and the buried columns and the drift region are arranged in an alternating manner.

公开(公告)号：US20190096992A1

公开(公告)日：2019-03-28

申请号：US16203669

申请日：2018-11-29

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Tsung-Yi Huang ,  Chu-Feng Chen

IPC: H01L29/06 ,  H01L21/266 ,  H01L29/10 ,  H01L29/78 ,  H01L21/324 ,  H01L21/265 ,  H01L29/66 ,  H01L21/225 ,  H01L29/40

Abstract: A high voltage MOS device includes: a first drift region with a first conductive type, a body region with a second conductive type, plural second drift regions with the second conductive type, a gate, a source region with the first conductive type, a drain with the first conductive type, and a body contact region with the second conductive type. The plural second drift regions contact the body region along the lateral direction, and are located separately in the width direction. Any neighboring two second drift regions do not contact each other. Each of the second drift regions is separated from the drain by the first drift region.

公开(公告)号：US10177220B2

公开(公告)日：2019-01-08

申请号：US15662277

申请日：2017-07-27

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Tsung-Yi Huang ,  Chu-Feng Chen

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L29/40 ,  H01L21/265 ,  H01L21/266 ,  H01L21/324 ,  H01L21/225 ,  H01L29/66

Abstract: A high voltage MOS device includes: a first drift region with a first conductive type, a body region with a second conductive type, plural second drift regions with the second conductive type, a gate, a source region with the first conductive type, a drain with the first conductive type, and a body contact region with the second conductive type. The plural second drift regions contact the body region along the lateral direction, and are located separately in the width direction. Any neighboring two second drift regions do not contact each other. Each of the second drift regions is separated from the drain by the first drift region.

公开(公告)号：US20180358432A1

公开(公告)日：2018-12-13

申请号：US15909989

申请日：2018-03-01

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Tsung-Yi Huang

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/0623 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/66681 ,  H01L29/7816

Abstract: A high-side device includes: a substrate, an epitaxial layer, a high voltage well, a body region, a gate, a source, a drain, two buried regions. A PN junction is formed between the body region and the high voltage well, wherein the PN junction is perpendicular to a channel direction. One buried region is formed in the epitaxial layer and has a first conductive type, wherein an inner side boundary thereof is located between the drain and the PN junction. The other buried region is formed in the substrate and in the epitaxial layer and has a second conductive type, wherein an inner side boundary thereof is located between the drain and the PN junction. The impurity concentration of the second buried region is sufficient to prevent the high voltage well between the PN junction and the drain from being completely depleted when the high-side power device is ON.

公开(公告)号：US20180342611A1

公开(公告)日：2018-11-29

申请号：US16038001

申请日：2018-07-17

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Tsung-Yi Huang

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L21/762 ,  H01L29/06 ,  H01L29/423

Abstract: A high-side device includes: a substrate, an epitaxial layer, a high voltage well, a body region, a gate, a source, a drain, and a buried region. A channel junction is formed between the body region and the high voltage well. The buried region is formed in the substrate and the epitaxial layer, and in a vertical direction, a part of the buried region is located in the substrate and another part of the buried region is located in the epitaxial layer. In the channel direction, an inner side boundary of the buried region is between the drain and the channel junction. An impurity concentration of a second conductive type of the buried region is sufficient to prevent the high voltage well between the channel junction and the drain from being completely depleted when the high-side power device operates in a conductive operation. A corresponding manufacturing method is also disclosed.

公开(公告)号：US10128373B2

公开(公告)日：2018-11-13

申请号：US15585949

申请日：2017-05-03

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Tsung-Yi Huang

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L23/535 ,  H01L21/768

Abstract: The present invention provides a MOS (Metal-Oxide-Silicon) device and a manufacturing method thereof. The MOS device includes: a semiconductor substrate, a gate, a source, a drain, and two LDDs (Lightly-Doped-Drains). At least one recess is formed at an upper surface of the semiconductor substrate. The recess has a depth which is deeper than the depth of the two LDDs. The recess is filled with a conductive material. A vertical connection portion is formed at a boundary of the recess in the vertical direction, to at least connect one of the LDDs to the drain. The LDD closer to the drain is not laterally in contact with the drain but is connected to the drain by the vertical direction.

公开(公告)号：US09853099B1

公开(公告)日：2017-12-26

申请号：US15490626

申请日：2017-04-18

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Tsung-Yi Huang ,  Chu-Feng Chen

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10

CPC classification number: H01L29/0611 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66681 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/7816

Abstract: The present invention provides a DMOS device and a manufacturing method thereof. The DMOS device includes: a substrate, an epitaxial layer, a high voltage well, a body region, a gate, a source, a drain, a drift buried region and a buried region. A first PN junction is formed between the high voltage well and an upper surface of the substrate. From a cross-section view, along the channel direction, a second PN junction is formed between the drift buried region and the buried region or formed between the high voltage well and the buried region. Along the channel direction, the first PN junction and the second PN junction have respective depths. The depth is defined as a distance extending from the upper face of the epitaxial layer downward along a vertical direction. The depth of the second PN junction is shallower than the depth of the first PN junction.

公开(公告)号：US09786776B2

公开(公告)日：2017-10-10

申请号：US15260599

申请日：2016-09-09

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Tsung-Yi Huang ,  Chien-Wei Chiu

IPC: H01L29/24 ,  H01L21/331 ,  H01L21/329 ,  H01L29/778 ,  H01L29/66 ,  H01L29/20 ,  H01L29/205 ,  H01L29/08 ,  H01L29/10 ,  H01L23/48 ,  H01L29/732 ,  H01L29/739 ,  H01L29/872

CPC classification number: H01L29/7787 ,  H01L23/481 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/0843 ,  H01L29/1004 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41708 ,  H01L29/4175 ,  H01L29/66212 ,  H01L29/66272 ,  H01L29/6631 ,  H01L29/66318 ,  H01L29/66333 ,  H01L29/66462 ,  H01L29/732 ,  H01L29/7395 ,  H01L29/7786 ,  H01L29/7788 ,  H01L29/872 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention discloses a vertical semiconductor device and a manufacturing method thereof. The vertical semiconductor device includes: a substrate having a first surface and a second surface, the substrate including a conductive array formed by multiple conductive plugs through the substrate; a semiconductor layer formed on the first surface, the semiconductor layer having a third surface and a fourth surface, wherein the fourth surface faces the first surface; a first electrode formed on the third surface; and a second electrode formed on the second surface for electrically connecting to the conductive array.

公开(公告)号：US09704987B2

公开(公告)日：2017-07-11

申请号：US15225559

申请日：2016-08-01

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Tsung-Yi Huang

IPC: H01L21/04 ,  H01L29/78 ,  H01L29/10 ,  H01L21/762 ,  H01L29/08 ,  H01L29/36 ,  H01L29/45 ,  H01L29/417 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/7816 ,  H01L21/76202 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0882 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/4175 ,  H01L29/456 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7835

Abstract: A lateral double diffused metal oxide semiconductor device, includes: a P-type substrate, an epitaxial layer, a P-type high voltage well, a P-type body region, an N-type well, an isolation oxide region, a drift oxide region, a gate, an N-type contact region, a P-type contact region, a top source, a bottom source, and an N-type drain. The P-type body region is between and connects the P-type high voltage well and the surface of the epitaxial layer. The P-type body region includes a peak concentration region, which is beneath and in direct contact the surface of the epitaxial layer, wherein the peak concentration region has a highest P-type impurity concentration in the P-type body region. The P-type impurity concentration of the P-type body region is higher than a predetermined threshold to suppress a parasitic bipolar transistor such that it does not turn ON.