公开(公告)号：US20050009209A1

公开(公告)日：2005-01-13

申请号：US10447209

申请日：2003-05-27

Applicant: Raffaele Zambrano

Inventor： Raffaele Zambrano

IPC: H01L21/02 ,  H01L21/8246 ,  H01L27/115 ,  H01L21/00

CPC classification number: H01L27/11502 ,  H01L27/11507 ,  H01L28/55

Abstract: A process for selectively sealing a capacitive element incorporated in a non-volatile memory cell integrated in a semiconductor substrate, the cell including a MOS transistor. The process includes: forming the MOS transistor on the semiconductor substrate; depositing an insulating layer over the substrate and MOS transistor; depositing a first metal layer to form, using a photolithographic technique, a lower electrode of the capacitive element; depositing a dielectric layer onto the first metal layer; depositing a second metal layer onto the dielectric layer; depositing a layer of a sealing material onto the second metal layer, the sealing material being impermeable to hydrogen; and defining the dielectric layer, second metal layer, and sealing layer by a single photolithographic defining step, so to form an upper electrode in the second metal layer and concurrently pattern the dielectric layer and seal the capacitive element.

Abstract translation: 一种用于选择性地密封结合在集成在半导体衬底中的非易失性存储单元中的电容元件的工艺，该电池包括MOS晶体管。 该工艺包括：在半导体衬底上形成MOS晶体管; 在衬底和MOS晶体管上沉积绝缘层; 使用光刻技术沉积第一金属层以形成电容元件的下电极; 在第一金属层上沉积介电层; 在所述电介质层上沉积第二金属层; 在第二金属层上沉积密封材料层，密封材料不可渗透氢; 并且通过单个光刻限定步骤限定电介质层，第二金属层和密封层，从而在第二金属层中形成上电极，同时对电介质层进行图案化并密封电容元件。

公开(公告)号：US06737284B2

公开(公告)日：2004-05-18

申请号：US10263361

申请日：2002-10-01

Applicant: Raffaele Zambrano

Inventor： Raffaele Zambrano

IPC: H01L2100

CPC classification number: H01L27/11502 ,  H01L21/76801 ,  H01L21/76837 ,  H01L21/76877 ,  H01L27/0629 ,  H01L27/1085 ,  H01L28/55 ,  H01L28/60 ,  H01L28/75

Abstract: A contact structure for semiconductor devices which are integrated on a semiconductor layer is provided. The structure comprises at least one MOS device and at least one capacitor element where the contact is provided at an opening formed in an insulating layer which overlies at least in part the semiconductor layer. Further, the opening has its surface edges, walls and bottom coated with a metal layer and filled with an insulating layer.

Abstract translation: 提供集成在半导体层上的用于半导体器件的接触结构。 该结构包括至少一个MOS器件和至少一个电容器元件，其中触点设置在形成在至少部分半导体层的绝缘层中的开口处。 此外，开口具有其表面边缘，壁和底部涂覆有金属层并且填充有绝缘层。

公开(公告)号：US06656801B2

公开(公告)日：2003-12-02

申请号：US09911637

申请日：2001-07-23

Applicant: Chiara Corvasce ,  Raffaele Zambrano

Inventor： Chiara Corvasce ,  Raffaele Zambrano

IPC: H01L21336

CPC classification number: H01L27/11502 ,  H01L27/10811 ,  H01L27/10888 ,  H01L27/115 ,  H01L27/11507

Abstract: The cells of the stacked type each comprise a MOS transistor formed in an active region of a substrate of semiconductor material and a capacitor formed above the active region; each MOS transistor has a first and a second conductive region and a control electrode and each capacitor has a first and a second plate separated by a dielectric region material, for example, ferroelectric one. The first conductive region of each MOS transistor is connected to the first plate of a respective capacitor, the second conductive region of each MOS transistor is connected to a respective bit line, the control electrode of each MOS transistor is connected to a respective word line, the second plate of each capacitor is connected to a respective plate line. The plate lines run perpendicular to the bit line and parallel to the word lines. At least two cells adjacent in a parallel direction to the bit lines share the same dielectric region material. In this way, the manufacturing process is not critical and the size of the cells is minimal.

Abstract translation: 层叠型电池单元包括形成在半导体材料的衬底的有源区和形成在有源区上方的电容器的MOS晶体管; 每个MOS晶体管具有第一和第二导电区域和控制电极，并且每个电容器具有由电介质区域材料（例如铁电体）隔开的第一和第二板。 每个MOS晶体管的第一导电区域连接到相应电容器的第一板，每个MOS晶体管的第二导电区域连接到相应的位线，每个MOS晶体管的控制电极连接到相应的字线， 每个电容器的第二板连接到相应的板线。 平板线垂直于位线延伸并平行于字线。 与位线平行方向相邻的至少两个单元共享相同的电介质区域材料。 以这种方式，制造过程不是关键的，并且电池的尺寸是最小的。

公开(公告)号：US06366488B1

公开(公告)日：2002-04-02

申请号：US09561331

申请日：2000-04-28

Applicant: Raffaele Zambrano ,  Chiara Corvasce

Inventor： Raffaele Zambrano ,  Chiara Corvasce

IPC: G11C1122

CPC classification number: H01L27/11502 ,  G11C11/22 ,  H01L27/11507

Abstract: Presented is a ferroelectric non-volatile memory cell in a semiconductor substrate that has a MOS device connected in parallel to a ferroelectric capacitor. The MOS device has first and second conduction terminals and is covered with an insulating layer. The ferroelectric capacitor has a lower electrode formed on the insulating layer above the first conduction terminals and are electrically coupled to them. The lower electrode of the ferroelectric capacitor is covered with a layer of ferroelectric material and coupled capacitively to an upper electrode. The upper electrode is formed above the second conduction terminals and are electrically connected thereto, and extends over the ferroelectric material to at least partially overlap the lower electrode. Also presented is a non-volatile memory matrix that includes a plurality of the ferroelectric memory cells that are organized into rows and columns.

Abstract translation: 本发明提供一种半导体衬底中的铁电非易失性存储单元，其具有与铁电电容器并联连接的MOS器件。 MOS器件具有第一和第二导电端子并被绝缘层覆盖。 铁电电容器具有在第一导电端子上方的绝缘层上形成的下电极，并与它们电连接。 铁电电容器的下电极被一层铁电材料覆盖并电容耦合到上电极。 上电极形成在第二导电端子的上方并与其电连接，并且在铁电材料上延伸至少部分地与下电极重叠。 还提出了包括被组织成行和列的多个铁电存储器单元的非易失性存储器矩阵。

公开(公告)号：US06362072B1

公开(公告)日：2002-03-26

申请号：US09431714

申请日：1999-10-26

Applicant: Raffaele Zambrano

Inventor： Raffaele Zambrano

IPC: H01L21762

CPC classification number: H01L21/763 ,  H01L21/76232

Abstract: A process for forming, on a semiconductor substrate, an isolation structure between two zones of an integrated circuit wherein active regions of electronic components integrated thereto have already been defined, comprises the steps of: defining an isolation region on a layer of silicon oxide overlying a silicon layer; selectively etching the silicon to provide the isolation region; growing thermal oxide over the interior surfaces of the isolation structure; depositing dielectric conformingly; and oxidizing the deposited dielectric.

Abstract translation: 一种在半导体衬底上形成集成电路的两个区域之间的隔离结构的工艺，其中已经定义了与其集成的电子元件的有源区域，其中包括以下步骤：在氧化硅层上界定隔离区域 硅层; 选择性地蚀刻硅以提供隔离区域; 在隔离结构的内表面上生长热氧化物; 沉积电介质; 并氧化沉积的电介质。

公开(公告)号：US6093948A

公开(公告)日：2000-07-25

申请号：US286638

申请日：1994-08-05

Applicant: Raffaele Zambrano ,  Carmelo Magro

Inventor： Raffaele Zambrano ,  Carmelo Magro

IPC: H01L21/336 ,  H01L29/10 ,  H01L29/78 ,  H01L29/76

CPC classification number: H01L29/66712 ,  H01L29/1095 ,  H01L29/7802 ,  Y10S148/126

Abstract: The process provides first for the accomplishment of low-doping body regions at the sides and under a gate region and then the accomplishment of high-doping body regions inside said low-doping body regions and self-aligned with said gate region. There is thus obtained an MOS power transistor with vertical current flow which has high-doping body regions self-aligned with said gate region and with a reduced junction depth.

Abstract translation: 该方法首先在侧面和栅极区域处实现低掺杂体区域，然后在所述低掺杂体区域内部实现高掺杂体区域并与所述栅极区域自对准。 因此获得了具有垂直电流的MOS功率晶体管，其具有与所述栅极区域自对准且具有减小的结深度的高掺杂体区域。

公开(公告)号：US6034400A

公开(公告)日：2000-03-07

申请号：US30149

申请日：1998-02-25

Applicant: Charles D. Waggoner ,  Antonio Imbruglia ,  Raffaele Zambrano

Inventor： Charles D. Waggoner ,  Antonio Imbruglia ,  Raffaele Zambrano

IPC: H01L27/04 ,  H01L21/822 ,  H01L27/02 ,  H03K19/0175 ,  H01L23/62 ,  H01L29/00

CPC classification number: H01L27/0251 ,  H01L2924/0002

Abstract: An MOS integrated circuit device with improved electrostatic protection capability includes high and low voltage rails for bringing externally-supplied power to points within the chip. Input bonding pads communicate input signals to the chip from external sources. Clamping circuitry connected to the input bonding pads clamps the input bonding pads to the low voltage rail during an electrostatic discharge event appearing on the input bonding pads. A receiver circuit is coupled to each input bonding pad. Each receiver circuit has a receiver input node, a receiver output node, and overvoltage-sensitive MOS circuitry between the input and output nodes. A conductor connects each input bonding pad to its receiver circuit. The conductor has a length greater than the distance between the input bonding pad and its receiver circuit. The conductor has an inductance sufficient to prevent high frequency components of ESD events received at an input bonding pad from reaching its receiver circuit. The conductor includes at least one fold for extending the length of the conductor to exceed the distance between the input bonding pad and the receiver input node.

Abstract translation: 具有改进的静电保护能力的MOS集成电路器件包括用于将外部供电的电源带到芯片内的高低压轨道。 输入接合焊盘从外部来源传送输入信号到芯片。 连接到输入接合焊盘的夹紧电路在输入接合焊盘出现静电放电事件期间将输入接合焊盘夹紧到低压轨道。 接收器电路耦合到每个输入接合焊盘。 每个接收器电路在输入和输出节点之间具有接收器输入节点，接收器输出节点和过电压敏感MOS电路。 导体将每个输入接合焊盘连接到其接收器电路。 导体的长度大于输入接合焊盘及其接收器电路之间的距离。 导体具有足以防止在输入接合焊盘处接收的ESD事件的高频分量到达其接收器电路的电感。 导体包括至少一个折叠，用于延长导体的长度以超过输入接合焊盘和接收器输入节点之间的距离。

公开(公告)号：US5986323A

公开(公告)日：1999-11-16

申请号：US549267

申请日：1995-10-27

Applicant: Raffaele Zambrano ,  Giuseppe Fallico

Inventor： Raffaele Zambrano ,  Giuseppe Fallico

IPC: H01L29/73 ,  H01L21/331 ,  H01L29/10 ,  H01L29/423 ,  H01L29/732 ,  H01L27/82 ,  H01L27/102 ,  H01L29/70 ,  H01L31/11

CPC classification number: H01L29/66272 ,  H01L29/1004 ,  H01L29/42304

Abstract: A high-frequency bipolar transistor structure includes a base region of a first conductivity type formed in a silicon layer of a second conductivity type, the base region comprising an intrinsic base region surrounded by an extrinsic base region, an emitter region of the second conductivity type formed inside the intrinsic base region, the extrinsic base region and the emitter region being contacted by a first polysilicon layer and a second polysilicon layer respectively. The first and the second polysilicon layers are respectively contacted by a base metal electrode and an emitter metal electrode. Between the extrinsic base region and the first polysilicon layer, a silicide layer is provided to reduce the extrinsic base resistance of the bipolar transistor.

Abstract translation: 高频双极晶体管结构包括形成在第二导电类型的硅层中的第一导电类型的基极区域，该基极区域包括被外部基极区域包围的本征基极区域，第二导电类型的发射极区域 形成在本征基区内，外基极区和发射极区分别与第一多晶硅层和第二多晶硅层接触。 第一和第二多晶硅层分别由基底金属电极和发射极金属电极接触。 在非本征基极区域和第一多晶硅层之间，提供硅化物层以降低双极晶体管的外部基极电阻。

公开(公告)号：US5838042A

公开(公告)日：1998-11-17

申请号：US622695

申请日：1996-03-26

Applicant: Raffaele Zambrano

Inventor： Raffaele Zambrano

IPC: H01L29/08 ,  H01L29/739 ,  H01L29/78 ,  H01L29/90

CPC classification number: H01L29/7395 ,  H01L29/0878 ,  H01L29/7802 ,  H01L29/1095

Abstract: A DMOS device structure includes a lightly doped semiconductor layer of a first conductivity type, a plurality of lightly doped semiconductor regions of a second conductivity type extending from a top surface of the lightly doped semiconductor layer thereinto, source regions of the first conductivity type contained in the lightly doped semiconductor regions and defining channel regions. The lightly doped semiconductor regions are contained in respective enhancement regions of the lightly doped semiconductor layer of the same conductivity type as, but with a lower resistivity than, the lightly doped semiconductor layer.

Abstract translation: DMOS器件结构包括第一导电类型的轻掺杂半导体层，从其中的轻掺杂半导体层的顶表面延伸的第二导电类型的多个轻掺杂半导体区域，第一导电类型的源极区包含在 轻掺杂的半导体区域和限定沟道区域。 轻掺杂半导体区域包含在相同导电类型的轻掺杂半导体层的相应增强区域中，但是具有比轻掺杂半导体层更低的电阻率。

公开(公告)号：US5703385A

公开(公告)日：1997-12-30

申请号：US443908

申请日：1995-05-17

Applicant: Raffaele Zambrano

Inventor： Raffaele Zambrano

IPC: H01L27/08 ,  H01L21/336 ,  H01L21/76 ,  H01L27/088 ,  H01L29/78 ,  H01L31/0328 ,  H01L23/58 ,  H01L29/76

CPC classification number: H01L27/088 ,  H01L2924/0002 ,  Y10S148/126

Abstract: A PIC structure includes a lightly doped semiconductor layer of the first conductivity type superimposed over a heavily doped semiconductor substrate of a second conductivity type, wherein a Vertical IGBT and a driving and control circuit including at least first conductivity type-channel MOSFETs are integrated. The MOSFETs are provided inside well regions of the second conductivity type which are included in at least one lightly doped region of the first conductivity type completely surrounded and isolated from the lightly doped layer of the first conductivity type by means of a respective isolated region of a second conductivity type.

Abstract translation: PIC结构包括叠加在第二导电类型的重掺杂半导体衬底上的第一导电类型的轻掺杂半导体层，其中垂直IGBT和包括至少第一导电类型沟道MOSFET的驱动和控制电路被集成。 所述MOSFET设置在所述第二导电类型的阱区域内，所述阱区域包括在所述第一导电类型的至少一个轻掺杂区域中，所述至少一个轻掺杂区域通过相应的隔离区域从所述第一导电类型的轻掺杂层完全包围和隔离 第二导电类型。