公开(公告)号：US07510926B2

公开(公告)日：2009-03-31

申请号：US11558982

申请日：2006-11-13

申请人： Andy Wei ,  Thorsten Kammler ,  Jan Hoentschel ,  Manfred Horstmann

发明人： Andy Wei ,  Thorsten Kammler ,  Jan Hoentschel ,  Manfred Horstmann

IPC分类号： H01L21/8238

CPC分类号： H01L29/66636 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/7848

摘要： A strained semiconductor material may be positioned in close proximity to the channel region of a transistor, such as an SOI transistor, while reducing or avoiding undue relaxation effects of metal silicides and extension implantations, thereby providing enhanced efficiency for the strain generation.

摘要翻译： 应变半导体材料可以位于诸如SOI晶体管的晶体管的沟道区域附近，同时减少或避免金属硅化物和延伸注入的不适当的松弛效应，从而为应变产生提供增强的效率。

公开(公告)号：US20080268597A1

公开(公告)日：2008-10-30

申请号：US11964211

申请日：2007-12-26

申请人： Andy Wei ,  Thomas Feudel ,  Casey Scott

发明人： Andy Wei ,  Thomas Feudel ,  Casey Scott

IPC分类号： H01L21/30 ,  H01L21/336

CPC分类号： H01L21/26513 ,  H01L21/268 ,  H01L21/823418 ,  H01L21/823814

摘要： By performing multiple radiation-based anneal processes on the basis of less critical process parameters, the overall risk for creating anneal-induced damage, such as melting of gate portions, may be substantially avoided while nevertheless the respective degree of dopant activation may be enhanced for each individual anneal process. Consequently, the sheet resistance of advanced transistor devices may be reduced with a decreasing number of sequential anneal processes.

摘要翻译： 通过基于不太关键的工艺参数进行多个基于辐射的退火工艺，可以基本上避免产生退火诱发的损伤（例如浇口部分的熔化）的总体风险，尽管可以增强各自的掺杂剂活化程度， 每个退火过程。 因此，先进的晶体管器件的薄层电阻可以随着连续退火工艺数量的减少而减小。

公开(公告)号：US20080182371A1

公开(公告)日：2008-07-31

申请号：US11778930

申请日：2007-07-17

申请人： Andreas Gehring ,  Maciej Wiatr ,  Andy Wei ,  Thorsten Kammler ,  Roman Boschke ,  Casey Scott

发明人： Andreas Gehring ,  Maciej Wiatr ,  Andy Wei ,  Thorsten Kammler ,  Roman Boschke ,  Casey Scott

IPC分类号： H01L21/8238

CPC分类号： H01L29/6656 ,  H01L21/823807 ,  H01L29/1087 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66636

摘要： By providing a protection layer on a silicon/germanium material of high germanium concentration, a corresponding loss of strained semiconductor material may be significantly reduced or even completely avoided. The protection layer may be formed prior to critical cleaning processes and may be maintained until the formation of metal silicide regions. Hence, high performance gain of P-type transistors may be accomplished without requiring massive overfill during the selective epitaxial growth process.

摘要翻译： 通过在高锗浓度的硅/锗材料上提供保护层，相应的应变半导体材料的损失可以显着降低甚至完全避免。 保护层可以在关键的清洁过程之前形成，并且可以保持直到形成金属硅化物区域。 因此，可以在选择性外延生长工艺期间不需要大量过量填充来实现P型晶体管的高性能增益。

公开(公告)号：US07402497B2

公开(公告)日：2008-07-22

申请号：US11551263

申请日：2006-10-20

申请人： Andy Wei ,  Thorsten Kammler ,  Jan Hoentschel ,  Manfred Horstmann

发明人： Andy Wei ,  Thorsten Kammler ,  Jan Hoentschel ,  Manfred Horstmann

IPC分类号： H01L21/336

CPC分类号： H01L21/26586 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

摘要： By removing a portion of a halo region or by avoiding the formation of the halo region within the extension region, which may be subsequently formed on the basis of a re-grown semiconductor material, the threshold roll off behavior may be significantly improved, wherein an enhanced current drive capability may simultaneously be achieved.

摘要翻译： 通过去除晕圈区域的一部分或通过避免在延伸区域内形成卤区，其可以随后基于重新生长的半导体材料形成，可以显着改善阈值滚降行为，其中 可以同时实现增强的电流驱动能力。

公开(公告)号：US07329571B2

公开(公告)日：2008-02-12

申请号：US11466802

申请日：2006-08-24

申请人： Jan Hoentschel ,  Andy Wei ,  Manfred Horstmann ,  Thorsten Kammler

发明人： Jan Hoentschel ,  Andy Wei ,  Manfred Horstmann ,  Thorsten Kammler

IPC分类号： H01L21/8238 ,  H01L21/336 ,  H01L21/44

CPC分类号： H01L21/84 ,  H01L21/823807 ,  H01L21/823864 ,  H01L27/1203 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/78618 ,  H01L29/78684

摘要： By combining a plurality of stress inducing mechanisms in each of different types of transistors, a significant performance gain may be obtained, thereby providing enhanced flexibility in adjusting product specific characteristics. For this purpose, sidewall spacers with high tensile stress may be commonly formed on PMOS and NMOS transistors, wherein a deleterious effect on the PMOS transistor may be compensated for by a corresponding compressively stressed contact etch stop layer, while the NMOS transistor comprises a contact etch stop layer with tensile stress. Furthermore, the PMOS transistor comprises an embedded strained semiconductor layer for efficiently creating compressive strain in the channel region.

摘要翻译： 通过在不同类型的晶体管中组合多个应力诱导机构，可以获得显着的性能增益，从而在调整产品特定特性方面提供增强的灵活性。 为此，可以在PMOS和NMOS晶体管上通常形成具有高拉伸应力的侧壁间隔物，其中可以通过相应的压缩应力接触蚀刻停止层补偿对PMOS晶体管的有害影响，而NMOS晶体管包括接触蚀刻 停止层拉伸应力。 此外，PMOS晶体管包括用于在沟道区域中有效地产生压缩应变的嵌入式应变半导体层。

公开(公告)号：US20070252205A1

公开(公告)日：2007-11-01

申请号：US11609995

申请日：2006-12-13

申请人： Jan Hoentschel ,  Andy Wei ,  Joe Bloomquist ,  Manfred Horstmann

发明人： Jan Hoentschel ,  Andy Wei ,  Joe Bloomquist ,  Manfred Horstmann

IPC分类号： H01L27/12 ,  H01L21/336

CPC分类号： H01L29/78609 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78621

摘要： By introducing a atomic species, such as carbon, fluorine and the like, into the drain and source regions, as well as in the body region, the junction leakage of SOI transistors may be significantly increased, thereby providing an enhanced leakage path for accumulated minority charge carriers. Consequently, fluctuations of the body potential may be significantly reduced, thereby improving the overall performance of advanced SOI devices. In particular embodiments, the mechanism may be selectively applied to threshold voltage sensitive device areas, such as static RAM areas.

摘要翻译： 通过将诸如碳，氟等的原子物质引入漏极和源极区域以及在体区域中，可以显着增加SOI晶体管的结漏电，从而为累积的少数族群提供增强的泄漏路径 电荷载体。 因此，体电位的波动可能会显着降低，从而提高先进的SOI器件的整体性能。 在特定实施例中，可以将机构选择性地应用于阈值电压敏感设备区域，例如静态RAM区域。

公开(公告)号：US20070123010A1

公开(公告)日：2007-05-31

申请号：US11530722

申请日：2006-09-11

申请人： Jan Hoentschel ,  Andy Wei ,  Mario Heinze ,  Peter Javorka

发明人： Jan Hoentschel ,  Andy Wei ,  Mario Heinze ,  Peter Javorka

IPC分类号： H01L21/336 ,  H01L21/20

CPC分类号： H01L21/2652 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/1033 ,  H01L29/1054 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7848

摘要： By performing a tilted amorphization implantation and a subsequent re-crystallization on the basis of a stressed overlying material, a highly efficient strain-inducing mechanism is provided. The tilted amorphization implantation may result in a significantly reduced defect rate during the re-crystallization process, thereby substantially reducing leakage currents in sophisticated transistor elements.

摘要翻译： 通过在受应力的上覆材料的基础上进行倾斜的非晶化注入和随后的重结晶，提供了一种高效的应变诱导机制。 倾斜的非晶化注入可导致在重结晶过程期间显着降低的缺陷率，从而大大降低复杂晶体管元件中的漏电流。

公开(公告)号：US20070096195A1

公开(公告)日：2007-05-03

申请号：US11466802

申请日：2006-08-24

申请人： Jan Hoentschel ,  Andy Wei ,  Manfred Horstmann ,  Thorsten Kammler

发明人： Jan Hoentschel ,  Andy Wei ,  Manfred Horstmann ,  Thorsten Kammler

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L21/84 ,  H01L21/823807 ,  H01L21/823864 ,  H01L27/1203 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/78618 ,  H01L29/78684

摘要： By combining a plurality of stress inducing mechanisms in each of different types of transistors, a significant performance gain may be obtained, thereby providing enhanced flexibility in adjusting product specific characteristics. For this purpose, sidewall spacers with high tensile stress may be commonly formed on PMOS and NMOS transistors, wherein a deleterious effect on the PMOS transistor may be compensated for by a corresponding compressively stressed contact etch stop layer, while the NMOS transistor comprises a contact etch stop layer with tensile stress. Furthermore, the PMOS transistor comprises an embedded strained semiconductor layer for efficiently creating compressive strain in the channel region.

摘要翻译： 通过在不同类型的晶体管中组合多个应力诱导机构，可以获得显着的性能增益，从而在调整产品特定特性方面提供增强的灵活性。 为此，可以在PMOS和NMOS晶体管上通常形成具有高拉伸应力的侧壁间隔物，其中可以通过相应的压缩应力接触蚀刻停止层补偿对PMOS晶体管的有害影响，而NMOS晶体管包括接触蚀刻 停止层拉伸应力。 此外，PMOS晶体管包括用于在沟道区域中有效地产生压缩应变的嵌入式应变半导体层。

公开(公告)号：US09450073B2

公开(公告)日：2016-09-20

申请号：US11936855

申请日：2007-11-08

申请人： Andy Wei ,  Thorsten Kammler ,  Roman Boschke ,  Casey Scott

发明人： Andy Wei ,  Thorsten Kammler ,  Roman Boschke ,  Casey Scott

IPC分类号： H01L27/12 ,  H01L29/66 ,  H01L29/78 ,  H01L21/762 ,  H01L21/84 ,  H01L29/417 ,  H01L29/786

CPC分类号： H01L29/6659 ,  H01L21/76264 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41766 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/78654

摘要： By reconfiguring material in a recess formed in drain and source regions of SOI transistors, the depth of the recess may be increased down to the buried insulating layer prior to forming respective metal silicide regions, thereby reducing series resistance and enhancing the stress transfer when the corresponding transistor element is covered by a highly stressed dielectric material. The material redistribution may be accomplished on the basis of a high temperature hydrogen bake.

摘要翻译： 通过在SOI晶体管的漏极和源极区域中形成的凹槽中重新配置材料，在形成相应的金属硅化物区域之前，可以将凹槽的深度增加到掩埋绝缘层，从而当对应的金属硅化物区域时减小串联电阻并增强应力传递 晶体管元件被高应力介电材料覆盖。 材料再分配可以基于高温氢气烘烤来实现。

公开(公告)号：US09023712B2

公开(公告)日：2015-05-05

申请号：US12052202

申请日：2008-03-20

申请人： Andy Wei ,  Roman Boschke ,  Markus Forsberg

发明人： Andy Wei ,  Roman Boschke ,  Markus Forsberg

IPC分类号： H01L21/00 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238

CPC分类号： H01L27/088 ,  H01L21/76224 ,  H01L21/82345 ,  H01L21/823481 ,  H01L21/823842 ,  H01L21/823878 ,  H01L23/528 ,  H01L23/53271 ,  H01L29/0653 ,  H01L29/1079 ,  H01L29/4238 ,  H01L2924/0002 ,  Y10S438/959 ,  Y10S438/975 ,  H01L2924/00

摘要： By forming a trench isolation structure after providing a high-k dielectric layer stack, direct contact of oxygen-containing insulating material of a top surface of the trench isolation structure with the high-k dielectric material in shared polylines may be avoided. This technique is self-aligned, thereby enabling further device scaling without requiring very tight lithography tolerances. After forming the trench isolation structure, the desired electrical connection across the trench isolation structure may be re-established by providing a further conductive material.

摘要翻译： 通过在提供高k电介质层堆叠之后形成沟槽隔离结构，可以避免沟槽隔离结构的顶表面中的含氧绝缘材料与共享折线中的高k电介质材料的直接接触。 这种技术是自对准的，从而能够进一步进行器件定标，而不需要非常严格的光刻公差。 在形成沟槽隔离结构之后，可以通过提供另外的导电材料来重新建立穿过沟槽隔离结构的期望的电连接。