摘要:
A DRAM memory cell and process sequence for fabricating a dense (20 or 18 square) layout is fabricated with silicon-on-insulator (SOI) CMOS technology. Specifically, the present invention provides a dense, high-performance SRAM cell replacement that is compatible with existing SOI CMOS technologies. Various gain cell layouts are known in the art. The present invention improves on the state of the art by providing a dense layout that is fabricated with SOI CMOS. In general terms, the memory cell includes a first transistor provided with a gate, a source, and a drain respectively; a second transistor having a first gate, a second gate, a source, and a drain respectively; and a capacitor having a first terminal, wherein the first terminal of said capacitor and the second gate of said second transistor comprise a single entity.
摘要:
A DRAM memory cell and process sequence for fabricating a dense (20 or 18 square) layout is fabricated with silicon-on-insulator (SOI) CMOS technology. Specifically, the present invention provides a dense, high-performance SRAM cell replacement that is compatible with existing SOI CMOS technologies. Various gain cell layouts are known in the art. The present invention improves on the state of the art by providing a dense layout that is fabricated with SOI CMOS. In general terms, the memory cell includes a first transistor provided with a gate, a source, and a drain respectively; a second transistor having a first gate, a second gate, a source, and a drain respectively; and a capacitor having a first terminal, wherein the first terminal of said capacitor and the second gate of said second transistor comprise a single entity.
摘要:
A semiconductor memory structure having a feature size of less than about 90 nm which exhibits little or no dynamic charge loss and little or no trap assisted junction leakage is provided. Specifically, the semiconductor structure includes at least one back-to-back pair of trench storage memory cells present in a Si-containing substrate. Each memory cell includes a vertical transistor overlaying a trench capacitor. Strap outdiffusions are present on each vertical sidewall of the trench storage memory cells so as to interconnect the vertical transistor and the trench capacitor of each memory cell to the Si-containing substrate. A punchthrough stop doping pocket is located between each back-to-back pair of trench storage memory cells and it is centered between the strap outdiffusions of adjacent storage trenches, and self-aligned to the adjacent storage trenches.
摘要:
A self-aligned shallow trench isolation region for a memory cell array is formed by etching a plurality of vertical deep trenches in a substrate and coating the trenches with an oxidation barrier layer. The oxidation barrier layer is recessed in portions of the trenches to expose portions of the substrate in the trenches. The exposed portions of the substrate are merged by oxidization into thermal oxide regions to form the self-aligned shallow trench isolation structure which isolates adjacent portions of substrate material. The merged oxide regions are self-aligned as they automatically aligned to the edges of the deep trenches when merged together to define the location of the isolation region within the memory cell array during IC fabrication. The instant self-aligned shallow trench isolation structure avoids the need for an isolation mask to separate or isolate the plurality of trenches within adjacent active area rows on a single substrate.
摘要:
An anti-fuse structure that can be programmed at low voltage and current and which potentially consumes very little chip spaces and can be formed interstitially between elements spaced by a minimum lithographic feature size is formed on a composite substrate such as a silicon-on-insulator wafer by etching a contact through an insulator to a support semiconductor layer, preferably in combination with formation of a capacitor-like structure reaching to or into the support layer. The anti-fuse may be programmed either by the selected location of conductor formation and/or damaging a dielectric of the capacitor-like structure. An insulating collar is used to surround a portion of either the conductor or the capacitor-like structure to confine damage to the desired location. Heating effects voltage and noise due to programming currents are effectively isolated to the bulk silicon layer, permitting programming during normal operation of the device. Thus the potential for self-repair without interruption of operation is realized.
摘要:
An isolation region for a memory array in which the isolation region includes at least one trench region having sidewalls that extend to a bottom surface and a slit region formed beneath the final trench region, wherein the slit region is narrower than the overlying trench regions and has a void formed intentionally therein is provided.
摘要:
A semiconductor structure is provided along with a corresponding method of producing such a structure. The method and structure may include providing a semiconductor substrate, a gate insulator over the semiconductor substrate, a conductor comprising intrinsic polysilicon over the gate insulator, a silicide layer over the polysilicon and an insulating cap over the silicide layer. Insulating spacers may be provided along sides of the silicide layer and the insulating cap. The polysilicon may be doped with a first conductive type dopant. The first conductive type dopant may be spread over the polysilicon to form a doped polysilicon layer. A gate sidewall layer may be formed on sides of the doped polysilicon layer. A bird's beak of the gate sidewall layer may also be formed in a corner of the polysilicon.
摘要:
An easily manufactured connecting structure from a node conductor of trench capacitor device is characterized at least in part by the presence of an isolation collar located above the node conductor, at least a portion of the collar having an exterior surface which is substantially conformal with at least a portion of an adjacent wall of the trench, a buried strap region in the trench above the node conductor, the strap region being bounded laterally by the isolation collar except at an opening in the collar. The connecting structure is preferably formed by a method involving clearing an isolation collar from a first interior surface of a deep trench at a location above a storage capacitor while leaving the isolation collar at other surfaces of the deep trench.
摘要:
A method for forming an isolation trench region in a semiconductor substrate includes providing the trench region in the semiconductor substrate, adding spacer material at least to sidewalls of the trench region, and etching the trench region at a bottom surface thereof to extend the trench region below the bottom surface and form a crevice region. The spacer material may be subsequently heated such that the spacer material flows from the sidewalls and into the crevice region.
摘要:
An integrated circuit is provided which includes a memory having multiple ports per memory cell for accessing a data bit within each of a plurality of the memory cells. Such memory includes an array of memory cells in which each memory cell includes a plurality of capacitors connected together as a unitary source of capacitance. A first access transistor is coupled between a first one of the plurality of capacitors and a first bitline and a second access transistor is coupled between a second one of the plurality of capacitors and a second bitline. In each memory cell, a gate of the first access transistor is connected to a first wordline and a gate of the second access transistor is connected to a second wordline.