公开(公告)号：US09769050B2

公开(公告)日：2017-09-19

申请号：US14581595

申请日：2014-12-23

申请人： Andrew J. Herdrich ,  Patrick Connor ,  Dinesh Kumar ,  Alexander W. Min ,  Ravishankar Iyer ,  Daniel J. Dahle ,  Kapil Sood ,  Jeffrey B. Shaw

发明人： Andrew J. Herdrich ,  Patrick Connor ,  Dinesh Kumar ,  Alexander W. Min ,  Ravishankar Iyer ,  Daniel J. Dahle ,  Kapil Sood ,  Jeffrey B. Shaw

IPC分类号： G06F15/173 ,  H04L12/26 ,  H04L12/24 ,  G06F12/084 ,  G06F12/0811

CPC分类号： H04L43/50 ,  G06F12/0811 ,  G06F12/084 ,  G06F2212/152 ,  G06F2212/601 ,  H04L41/0896 ,  H04L41/5009 ,  H04L41/5025 ,  H04L41/5035 ,  H04L41/5096 ,  H04L43/16

摘要： In embodiments, apparatuses, methods and storage media (transitory and non-transitory) are described that are associated with end-to-end datacenter performance control. In various embodiments, an apparatus for computing may receive a datacenter performance target, determine an end-to-end datacenter performance level based at least in part on quality of service data collected from a plurality of nodes, and send a mitigation command based at least in part on a result of a comparison of the end-to-end datacenter performance level determined to the datacenter performance target. In various embodiments, the apparatus for computing may include one or more processors, a memory, a datacenter performance monitor to receive a datacenter performance target corresponding to a service level agreement, and a mitigation module to send a mitigation command based at least in part on a result of a comparison of an end-to-end datacenter performance level to a datacenter performance target.

公开(公告)号：US20140240326A1

公开(公告)日：2014-08-28

申请号：US13780117

申请日：2013-02-28

申请人： Daniel F. Cutter ,  Blaise Fanning ,  Ramadass Nagarajan ,  Ravishankar Iyer ,  Quang T. Le ,  Ravi Kolagotla ,  Ioannis T. Schoinas ,  Jose S. Niell

发明人： Daniel F. Cutter ,  Blaise Fanning ,  Ramadass Nagarajan ,  Ravishankar Iyer ,  Quang T. Le ,  Ravi Kolagotla ,  Ioannis T. Schoinas ,  Jose S. Niell

IPC分类号： G06F3/06

CPC分类号： G06F13/00 ,  G06F9/00 ,  G06F13/1626 ,  Y02D10/14

摘要： In an embodiment, a shared memory fabric is configured to receive memory requests from multiple agents, where at least some of the requests have an associated order identifier and a deadline value to indicate a maximum latency prior to completion of the memory request. Responsive to the requests, the fabric is to arbitrate between the requests based at least in part on the deadline values. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，共享存储器结构被配置为从多个代理接收存储器请求，其中至少一些请求具有相关联的顺序标识符和在存储器请求完成之前指示最大等待时间的最后期限值。 响应于请求，结构是至少部分地基于期限值来在请求之间进行仲裁。 描述和要求保护其他实施例。

公开(公告)号：US20140201471A1

公开(公告)日：2014-07-17

申请号：US13743795

申请日：2013-01-17

申请人： Daniel F. Cutter ,  Blaise Fanning ,  Ramadass Nagarajan ,  Jose S. Niell ,  Debra Bernstein ,  Deepak Limaye ,  Ioannis T. Schoinas ,  Ravishankar Iyer

发明人： Daniel F. Cutter ,  Blaise Fanning ,  Ramadass Nagarajan ,  Jose S. Niell ,  Debra Bernstein ,  Deepak Limaye ,  Ioannis T. Schoinas ,  Ravishankar Iyer

IPC分类号： G06F13/16

CPC分类号： G06F13/1663 ,  G06F13/1605 ,  G06F13/161 ,  G06F2212/1024 ,  G06F2213/0064 ,  Y02D10/14

摘要： In an embodiment, a shared memory fabric is configured to receive memory requests from multiple agents, where at least some of the requests have an associated deadline value to indicate a maximum latency prior to completion of the memory request. Responsive to the requests, the fabric is to arbitrate between the requests based at least in part on the deadline values. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，共享存储器结构被配置为从多个代理接收存储器请求，其中至少一些请求具有关联的最终期限值，以在完成存储器请求之前指示最大等待时间。 响应于请求，结构是至少部分地基于期限值来在请求之间进行仲裁。 描述和要求保护其他实施例。

公开(公告)号：US08781234B2

公开(公告)日：2014-07-15

申请号：US12896077

申请日：2010-10-01

申请人： Yong Zhang ,  Ravishankar Iyer ,  Rameshkumar G. Illikkal ,  Donald K. Newell ,  Jianping Zhou

发明人： Yong Zhang ,  Ravishankar Iyer ,  Rameshkumar G. Illikkal ,  Donald K. Newell ,  Jianping Zhou

IPC分类号： G06K9/50 ,  G06K9/46 ,  G06K9/62 ,  G06K9/66

CPC分类号： G06K9/481 ,  G06K9/00973 ,  G06K9/4671 ,  G06K2009/485

摘要： Methods and systems of recognizing images may include an apparatus having a hardware module with logic to, for a plurality of vectors in an image, determine a first intermediate computation based on even pixels of an image vector, and determine a second intermediate computation based on odd pixels of an image vector. The logic can also combine the first and second intermediate computations into a Hessian matrix computation.

摘要翻译： 识别图像的方法和系统可以包括具有硬件模块的装置，该硬件模块具有对于图像中的多个向量的逻辑，基于图像矢量的偶数像素确定第一中间计算，并且基于奇数来确定第二中间计算 图像矢量的像素。 逻辑还可以将第一和第二中间计算组合成Hessian矩阵计算。

公开(公告)号：US20140189704A1

公开(公告)日：2014-07-03

申请号：US13730539

申请日：2012-12-28

申请人： Paolo Narvaez ,  Ganapati N. Srinivasa ,  Eugene Gorbatov ,  Dheeraj R. Subbareddy ,  Mishali Naik ,  Alon Naveh ,  Abirami Prabhakaran ,  Eliezer Weissmann ,  David A. Koufaty ,  Paul Brett ,  Scott D. Hahn ,  Andrew J. Herdrich ,  Ravishankar Iyer ,  Nagabhushan Chitlur ,  Inder M. Sodhi ,  Gaurav Khanna ,  Russell J. Fenger

发明人： Paolo Narvaez ,  Ganapati N. Srinivasa ,  Eugene Gorbatov ,  Dheeraj R. Subbareddy ,  Mishali Naik ,  Alon Naveh ,  Abirami Prabhakaran ,  Eliezer Weissmann ,  David A. Koufaty ,  Paul Brett ,  Scott D. Hahn ,  Andrew J. Herdrich ,  Ravishankar Iyer ,  Nagabhushan Chitlur ,  Inder M. Sodhi ,  Gaurav Khanna ,  Russell J. Fenger

IPC分类号： G06F9/50

CPC分类号： G06F9/5044 ,  G06F9/45533 ,  G06F9/5077 ,  G06F9/5094 ,  G06F15/80 ,  Y02D10/22

摘要： A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a first set of one or more physical processor cores having first processing characteristics; a second set of one or more physical processor cores having second processing characteristics different from the first processing characteristics; virtual-to-physical (V-P) mapping logic to expose a plurality of virtual processors to software, the plurality of virtual processors to appear to the software as a plurality of homogeneous processor cores, the software to allocate threads to the virtual processors as if the virtual processors were homogeneous processor cores; wherein the V-P mapping logic is to map each virtual processor to a physical processor within the first set of physical processor cores or the second set of physical processor cores such that a thread allocated to a first virtual processor by software is executed by a physical processor mapped to the first virtual processor from the first set or the second set of physical processors.

摘要翻译： 描述异构处理器架构。 例如，根据本发明的一个实施例的处理器包括：具有第一处理特性的一个或多个物理处理器核心的第一组; 具有不同于所述第一处理特性的第二处理特性的第二组一个或多个物理处理器核; 虚拟到物理（VP）映射逻辑，以将多个虚拟处理器暴露给软件，所述多个虚拟处理器将软件呈现为多个同构的处理器核，所述软件将线程分配给虚拟处理器，如同 虚拟处理器是同类处理器核心; 其中所述VP映射逻辑将每个虚拟处理器映射到所述第一物理处理器核心集合或所述第二物理处理器核心组内的物理处理器，使得通过软件分配给第一虚拟处理器的线程由物理处理器映射执行 从第一组或第二组物理处理器到第一虚拟处理器。

公开(公告)号：US08364862B2

公开(公告)日：2013-01-29

申请号：US12482614

申请日：2009-06-11

申请人： Michael J. Espig ,  Zhen Fang ,  Ravishankar Iyer ,  David J. Harriman

发明人： Michael J. Espig ,  Zhen Fang ,  Ravishankar Iyer ,  David J. Harriman

IPC分类号： G06F3/00

CPC分类号： G06F13/24 ,  G06F9/542

摘要： In one embodiment, the present invention includes a method for handling a registration message received from a host processor, where the registration message delegates a poll operation with respect to a device from the host processor to another component. Information from the message may be stored in a poll table, and the component may send a read request to poll the device and report a result of the poll to the host processor based on a state of the device. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明包括一种用于处理从主机处理器接收的注册消息的方法，其中所述注册消息将关于设备的轮询操作从主机处理器委托给另一个组件。 来自消息的信息可以存储在轮询表中，并且组件可以发送读请求以轮询该设备并且基于该设备的状态向轮询处理器报告轮询的结果。 描述和要求保护其他实施例。

公开(公告)号：US07490191B2

公开(公告)日：2009-02-10

申请号：US11525980

申请日：2006-09-22

申请人： Rameshkumar G. Illikkal ,  Donald K. Newell ,  Ravishankar Iyer ,  Srihari Makineni

发明人： Rameshkumar G. Illikkal ,  Donald K. Newell ,  Ravishankar Iyer ,  Srihari Makineni

IPC分类号： G06F12/10

CPC分类号： G06F12/1036 ,  G06F12/0284 ,  G06F12/109 ,  G06F2212/656

摘要： Embodiments of apparatuses, methods, and systems for sharing information between guests in a virtual machine environment are disclosed. In one embodiment, an apparatus includes virtual machine control logic, an execution unit, and a memory management unit. The virtual machine control logic is to transfer control of the apparatus among a host and its guests. The execution unit is to execute an instruction to copy information from a virtual memory address in one guest's virtual address space to a virtual memory address in another guest's virtual address space. The memory management unit is to translate the virtual memory addresses to physical memory addresses.

摘要翻译： 公开了在虚拟机环境中在客人之间共享信息的装置，方法和系统的实施例。 在一个实施例中，装置包括虚拟机控制逻辑，执行单元和存储器管理单元。 虚拟机控制逻辑是在主机及其客人之间传送设备的控制。 执行单元执行将来自虚拟地址空间中的虚拟存储器地址的信息复制到另一访客虚拟地址空间中的虚拟存储器地址的指令。 内存管理单元将虚拟内存地址转换为物理内存地址。

公开(公告)号：US20050246500A1

公开(公告)日：2005-11-03

申请号：US10834593

申请日：2004-04-28

申请人： Ravishankar Iyer ,  Srihari Makineni ,  Ram Huggahalli

发明人： Ravishankar Iyer ,  Srihari Makineni ,  Ram Huggahalli

IPC分类号： G06F12/00 ,  G06F12/08

CPC分类号： G06F12/0862

摘要： In some embodiments, a method, apparatus and system for an application-aware cache push agent. In this regard, a cache push agent is introduced to push contents of memory into a cache of a processor in response to a memory read by the processor of associated contents. Other embodiments are described and claimed.

摘要翻译： 在一些实施例中，一种用于应用感知高速缓存推送代理的方法，装置和系统。 在这方面，引入缓存推送代理以响应于由处理器读取相关内容的存储器来将存储器的内容推送到处理器的高速缓存中。 描述和要求保护其他实施例。

公开(公告)号：US20050114605A1

公开(公告)日：2005-05-26

申请号：US10722884

申请日：2003-11-26

申请人： Ravishankar Iyer

发明人： Ravishankar Iyer

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0888

摘要： Methods and apparatus to process cache allocation requests are disclosed. In an example method, a priority level is assigned to a cache allocation request. Based on the priority level, an allocation probability associated with the cache allocation request is identified. Based on the allocation probability, the cache allocation request is identified with either an allocate condition and a bypass condition.

摘要翻译： 公开了处理高速缓存分配请求的方法和装置。 在示例性方法中，将优先级分配给高速缓存分配请求。 基于优先级，识别与高速缓存分配请求相关联的分配概率。 基于分配概率，使用分配条件和旁路条件来识别高速缓存分配请求。

公开(公告)号：US20220012592A1

公开(公告)日：2022-01-13

申请号：US17483693

申请日：2021-09-23

申请人： Nilesh Jain ,  Menachem Adelman ,  Raanan Sade ,  Ravishankar Iyer ,  Rajesh Poornachandran ,  Yash Akhauri

发明人： Nilesh Jain ,  Menachem Adelman ,  Raanan Sade ,  Ravishankar Iyer ,  Rajesh Poornachandran ,  Yash Akhauri

IPC分类号： G06N3/08 ,  H03M7/30 ,  G06F17/16

摘要： Methods, apparatus, systems, and articles of manufacture to perform weight and activation compression and decompression are disclosed. An example apparatus includes memory, instructions in the apparatus, and processor circuitry to execute the instructions to execute a compression operation to obtain compressed data corresponding to weights in a weight matrix, and determine meta-data associated with the weight matrix, a first portion of the meta-data indicative of whether the weight matrix is compressed, a second portion of the meta-data indicative of a cache size of the compressed data, and a third portion of the meta-data indicative of the compression operation executed to obtain the compressed data.