公开(公告)号：US20140001519A1

公开(公告)日：2014-01-02

申请号：US13538985

申请日：2012-06-29

申请人： Gilbert Dewey ,  Marko Radosavljevic ,  Ravi Pillarisetty ,  Benjamin Chu-Kung ,  Niloy Mukherjee

发明人： Gilbert Dewey ,  Marko Radosavljevic ,  Ravi Pillarisetty ,  Benjamin Chu-Kung ,  Niloy Mukherjee

IPC分类号： H01L29/78 ,  H01L21/762

CPC分类号： H01L29/1054 ,  H01L21/76224 ,  H01L29/66795 ,  H01L29/785

摘要： A fin is formed over a first barrier layer over a substrate. The first barrier layer has a band gap greater than the band gap of the fin. In one embodiment, a gate dielectric layer is deposited on the top surface and opposing sidewalls of the fin and is adjacent to a second barrier layer deposited on the first barrier layer underneath the fin. In one embodiment, the gate dielectric layer is deposited on the top surface and the opposing sidewalls of the fin and an isolating layer is formed adjacent to the first barrier layer underneath the fin. In one embodiment, the gate dielectric layer is deposited on the top surface and the opposing sidewalls of the fin, and an isolating layer is formed adjacent to the second barrier layer deposited between the fin and the first barrier layer.

摘要翻译： 翅片形成在衬底上的第一阻挡层上。 第一阻挡层的带隙大于翅片的带隙。 在一个实施例中，栅极电介质层沉积在鳍的顶表面和相对侧壁上，并且与沉积在鳍下方的第一阻挡层上的第二势垒层相邻。 在一个实施例中，栅极电介质层沉积在顶表面上，翅片的相对的侧壁和隔离层邻近鳍片下方的第一阻挡层形成。 在一个实施例中，栅极电介质层沉积在鳍的顶表面和相对侧壁上，隔离层形成在沉积在鳍与第一阻挡层之间的第二势垒层附近。

公开(公告)号：US08901537B2

公开(公告)日：2014-12-02

申请号：US12975278

申请日：2010-12-21

申请人： Anand S. Murthy ,  Glenn A. Glass ,  Tahir Ghani ,  Ravi Pillarisetty ,  Niloy Mukherjee ,  Jack T. Kavalieros ,  Roza Kotlyar ,  Willy Rachmady ,  Mark Y. Liu

发明人： Anand S. Murthy ,  Glenn A. Glass ,  Tahir Ghani ,  Ravi Pillarisetty ,  Niloy Mukherjee ,  Jack T. Kavalieros ,  Roza Kotlyar ,  Willy Rachmady ,  Mark Y. Liu

IPC分类号： H01L21/285 ,  H01L29/165 ,  H01L29/167 ,  H01L29/49 ,  H01L29/78 ,  H01L29/66 ,  H01L29/45

CPC分类号： H01L29/0676 ,  H01L21/02532 ,  H01L21/28512 ,  H01L21/28525 ,  H01L21/3215 ,  H01L21/76831 ,  H01L23/535 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0615 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/165 ,  H01L29/167 ,  H01L29/36 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/456 ,  H01L29/4966 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66681 ,  H01L29/66931 ,  H01L29/7785 ,  H01L29/78 ,  H01L29/7816 ,  H01L29/7833 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

摘要： Techniques are disclosed for forming transistor devices having source and drain regions with high concentrations of boron doped germanium. In some embodiments, an in situ boron doped germanium, or alternatively, boron doped silicon germanium capped with a heavily boron doped germanium layer, are provided using selective epitaxial deposition in the source and drain regions and their corresponding tip regions. In some such cases, germanium concentration can be, for example, in excess of 50 atomic % and up to 100 atomic %, and the boron concentration can be, for instance, in excess of 1E20 cm−3. A buffer providing graded germanium and/or boron concentrations can be used to better interface disparate layers. The concentration of boron doped in the germanium at the epi-metal interface effectively lowers parasitic resistance without degrading tip abruptness. The techniques can be embodied, for instance, in planar or non-planar transistor devices.

摘要翻译： 公开了用于形成具有高掺杂硼掺杂锗的源区和漏区的晶体管器件的技术。 在一些实施例中，使用在源极和漏极区域及其对应的尖端区域中的选择性外延沉积来提供原位硼掺杂锗或者掺杂有硼掺杂锗层的硼掺杂硅锗。 在一些这样的情况下，锗浓度可以例如超过50原子％且高达100原子％，并且硼浓度可以例如超过1E20cm-3。 可以使用提供梯度锗和/或硼浓度的缓冲液来更好地接合不同的层。 锗在外延金属界面掺杂的硼的浓度有效地降低了寄生电阻而不降低尖端突然性。 这些技术可以例如在平面或非平面晶体管器件中实现。

公开(公告)号：US09748338B2

公开(公告)日：2017-08-29

申请号：US13538985

申请日：2012-06-29

申请人： Gilbert Dewey ,  Marko Radosavljevic ,  Ravi Pillarisetty ,  Benjamin Chu-Kung ,  Niloy Mukherjee

发明人： Gilbert Dewey ,  Marko Radosavljevic ,  Ravi Pillarisetty ,  Benjamin Chu-Kung ,  Niloy Mukherjee

IPC分类号： H01L29/78 ,  H01L21/762 ,  H01L29/10 ,  H01L29/66

CPC分类号： H01L29/1054 ,  H01L21/76224 ,  H01L29/66795 ,  H01L29/785

摘要： A fin is formed over a first barrier layer over a substrate. The first barrier layer has a band gap greater than the band gap of the fin. In one embodiment, a gate dielectric layer is deposited on the top surface and opposing sidewalls of the fin and is adjacent to a second barrier layer deposited on the first barrier layer underneath the fin. In one embodiment, the gate dielectric layer is deposited on the top surface and the opposing sidewalls of the fin and an isolating layer is formed adjacent to the first barrier layer underneath the fin. In one embodiment, the gate dielectric layer is deposited on the top surface and the opposing sidewalls of the fin, and an isolating layer is formed adjacent to the second barrier layer deposited between the fin and the first barrier layer.

公开(公告)号：US09240410B2

公开(公告)日：2016-01-19

申请号：US13976413

申请日：2011-12-19

申请人： Han Wui Then ,  Robert Chau ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Jack Kavalieros ,  Matthew Metz ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Marko Radosavljevic

发明人： Han Wui Then ,  Robert Chau ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Jack Kavalieros ,  Matthew Metz ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Marko Radosavljevic

IPC分类号： H01L27/088 ,  H01L29/66 ,  H01L29/775 ,  H01L29/778 ,  H01L29/786 ,  H01L29/78 ,  B82Y10/00 ,  H01L29/06 ,  H01L29/20

CPC分类号： H01L29/158 ,  B82Y10/00 ,  H01L21/02603 ,  H01L23/66 ,  H01L27/0605 ,  H01L27/0886 ,  H01L29/045 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66469 ,  H01L29/66522 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/778 ,  H01L29/7786 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78681 ,  H01L29/78696 ,  H01L2223/6677 ,  Y10S977/938

摘要： A group III-N nanowire is disposed on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first group III-N material, a source region electrically coupled with a first end of the channel region, and a drain region electrically coupled with a second end of the channel region. A second group III-N material on the first group III-N material serves as a charge inducing layer, and/or barrier layer on surfaces of nanowire. A gate insulator and/or gate conductor coaxially wraps completely around the nanowire within the channel region. Drain and source contacts may similarly coaxially wrap completely around the drain and source regions.

公开(公告)号：US20140332852A1

公开(公告)日：2014-11-13

申请号：US14340981

申请日：2014-07-25

申请人： Gilbert Dewey ,  Marko Radosavljevic ,  Ravi Pillarisetty ,  Benjamin Chu-Kung ,  Niloy Mukherjee

发明人： Gilbert Dewey ,  Marko Radosavljevic ,  Ravi Pillarisetty ,  Benjamin Chu-Kung ,  Niloy Mukherjee

IPC分类号： H01L29/40 ,  H01L29/423 ,  H01L29/205 ,  H01L29/78 ,  H01L29/51

CPC分类号： H01L29/0673 ,  B82Y10/00 ,  B82Y99/00 ,  H01L29/0665 ,  H01L29/201 ,  H01L29/205 ,  H01L29/408 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/511 ,  H01L29/512 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66462 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785 ,  H01L29/78696

摘要： Non-planar semiconductor devices having group III-V material active regions with multi-dielectric gate stacks are described. For example, a semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a three-dimensional group III-V material body with a channel region. A source and drain material region is disposed above the three-dimensional group III-V material body. A trench is disposed in the source and drain material region separating a source region from a drain region, and exposing at least a portion of the channel region. A gate stack is disposed in the trench and on the exposed portion of the channel region. The gate stack includes first and second dielectric layers and a gate electrode.

公开(公告)号：US20130279145A1

公开(公告)日：2013-10-24

申请号：US13976413

申请日：2011-12-19

申请人： Han Wui Then ,  Robert Chau ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Jack Kavalieros ,  Matthew Metz ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Marko Radosavljevic

发明人： Han Wui Then ,  Robert Chau ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Jack Kavalieros ,  Matthew Metz ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Marko Radosavljevic

IPC分类号： H01L29/778 ,  H01L29/66

CPC分类号： H01L29/158 ,  B82Y10/00 ,  H01L21/02603 ,  H01L23/66 ,  H01L27/0605 ,  H01L27/0886 ,  H01L29/045 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66469 ,  H01L29/66522 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/778 ,  H01L29/7786 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78681 ,  H01L29/78696 ,  H01L2223/6677 ,  Y10S977/938

摘要： A group III-N nanowire is disposed on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first group III-N material, a source region electrically coupled with a first end of the channel region, and a drain region electrically coupled with a second end of the channel region. A second group III-N material on the first group III-N material serves as a charge inducing layer, and/or barrier layer on surfaces of nanowire. A gate insulator and/or gate conductor coaxially wraps completely around the nanowire within the channel region. Drain and source contacts may similarly coaxially wrap completely around the drain and source regions.

摘要翻译： III-N族纳米线设置在基板上。 纳米线的纵向长度被限定为第一组III-N材料的沟道区域，与沟道区域的第一端电耦合的源极区域和与沟道区域的第二端电耦合的漏极区域。 第一组III-N材料上的第二组III-N材料用作纳米线表面上的电荷诱导层和/或阻挡层。 栅极绝缘体和/或栅极导体在通道区域内的纳米线周围同轴地包裹。 排水和源极接触件可以类似地同轴地围绕漏极和源极区域包裹。

公开(公告)号：US20160240612A1

公开(公告)日：2016-08-18

申请号：US15135262

申请日：2016-04-21

申请人： Gilbert Dewey ,  Marko Radosavljevic ,  Ravi Pillarisetty ,  Benjamin Chu-Kung ,  Niloy Mukherjee

发明人： Gilbert Dewey ,  Marko Radosavljevic ,  Ravi Pillarisetty ,  Benjamin Chu-Kung ,  Niloy Mukherjee

IPC分类号： H01L29/06 ,  H01L29/66 ,  H01L29/423 ,  H01L29/51 ,  H01L29/201 ,  H01L29/205

CPC分类号： H01L29/0673 ,  B82Y10/00 ,  B82Y99/00 ,  H01L29/0665 ,  H01L29/201 ,  H01L29/205 ,  H01L29/408 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/511 ,  H01L29/512 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66462 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785 ,  H01L29/78696

摘要： Non-planar semiconductor devices having group III-V material active regions with multi-dielectric gate stacks are described. For example, a semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a three dimensional group III-V material body with a channel region. A source and drain material region is disposed above the three-dimensional group III-V material body. A trench is disposed in the source and drain material region separating a source region from a drain region, and exposing at least a portion of the channel region. A gate stack is disposed in the trench and on the exposed portion of the channel region. The gate stack includes first and second dielectric layers and a gate electrode.

摘要翻译： 描述具有多电介质栅叠层的具有III-V族材料的区域的非平面半导体器件。 例如，半导体器件包括设置在衬底上的异质结构。 异质结构包括具有沟道区的三维III-V族材料体。 源极和漏极材料区域设置在三维III-V族材料体上方。 在源极和漏极材料区域中布置沟槽，其将源极区域与漏极区域分离，并且暴露沟道区域的至少一部分。 栅极堆叠设置在沟槽中和沟道区域的暴露部分上。 栅极堆叠包括第一和第二电介质层和栅电极。

公开(公告)号：US20140084343A1

公开(公告)日：2014-03-27

申请号：US13629154

申请日：2012-09-27

申请人： Gilbert Dewey ,  Marko Radosavljevic ,  Ravi Pillarisetty ,  Benjamin Chu-Kung ,  Niloy Mukherjee

发明人： Gilbert Dewey ,  Marko Radosavljevic ,  Ravi Pillarisetty ,  Benjamin Chu-Kung ,  Niloy Mukherjee

IPC分类号： H01L29/78 ,  B82Y99/00

CPC分类号： H01L29/0673 ,  B82Y10/00 ,  B82Y99/00 ,  H01L29/0665 ,  H01L29/201 ,  H01L29/205 ,  H01L29/408 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/511 ,  H01L29/512 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66462 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785 ,  H01L29/78696

摘要： Non-planar semiconductor devices having group III-V material active regions with multi-dielectric gate stacks are described. For example, a semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a three-dimensional group III-V material body with a channel region. A source and drain material region is disposed above the three-dimensional group III-V material body. A trench is disposed in the source and drain material region separating a source region from a drain region, and exposing at least a portion of the channel region. A gate stack is disposed in the trench and on the exposed portion of the channel region. The gate stack includes first and second dielectric layers and a gate electrode.

摘要翻译： 描述具有多电介质栅叠层的具有III-V族材料的区域的非平面半导体器件。 例如，半导体器件包括设置在衬底上的异质结构。 异质结构包括具有沟道区的三维III-V族材料体。 源极和漏极材料区域设置在三维III-V族材料体上方。 在源极和漏极材料区域中布置沟槽，其将源极区域与漏极区域分离，并且暴露沟道区域的至少一部分。 栅极堆叠设置在沟槽中和沟道区域的暴露部分上。 栅极堆叠包括第一和第二电介质层和栅电极。

公开(公告)号：US20130307513A1

公开(公告)日：2013-11-21

申请号：US13976414

申请日：2011-12-19

申请人： Han Wui Then ,  Robert Chau ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Jack Kavalieros ,  Matthew Metz ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Marko Radosavljevic

发明人： Han Wui Then ,  Robert Chau ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Jack Kavalieros ,  Matthew Metz ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Marko Radosavljevic

IPC分类号： H01L29/775 ,  G05F3/02 ,  H01L29/66

CPC分类号： H01L29/0673 ,  B82Y10/00 ,  G05F3/02 ,  H01L21/02603 ,  H01L21/02636 ,  H01L21/225 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/31 ,  H01L21/31116 ,  H01L21/32133 ,  H01L21/324 ,  H01L29/04 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/2003 ,  H01L29/41725 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66462 ,  H01L29/66469 ,  H01L29/775 ,  H01L29/78696

摘要： Transistors suitable for high voltage and high frequency operation. A nanowire is disposed vertically or horizontally on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first semiconductor material, a source region electrically coupled with a first end of the channel region, a drain region electrically coupled with a second end of the channel region, and an extrinsic drain region disposed between the channel region and drain region. The extrinsic drain region has a wider bandgap than that of the first semiconductor. A gate stack including a gate conductor and a gate insulator coaxially wraps completely around the channel region, drain and source contacts similarly coaxially wrap completely around the drain and source regions.

摘要翻译： 晶体管适用于高电压和高频工作。 纳米线垂直或水平地布置在基底上。 纳米线的纵向长度被限定为第一半导体材料的沟道区域，与沟道区域的第一端电耦合的源极区域，与沟道区域的第二端电耦合的漏极区域和外部漏极 区域设置在沟道区域和漏极区域之间。 外在漏极区具有比第一半导体更宽的带隙。 包括栅极导体和栅极绝缘体的栅极堆叠器完全同轴地包裹在沟道区域周围，漏极和源极触点类似地同轴地围绕漏极和源极区域包裹。

公开(公告)号：US09245989B2

公开(公告)日：2016-01-26

申请号：US13976414

申请日：2011-12-19

申请人： Han Wui Then ,  Robert Chau ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Jack Kavalieros ,  Matthew Metz ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Marko Radosavljevic

发明人： Han Wui Then ,  Robert Chau ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Jack Kavalieros ,  Matthew Metz ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Marko Radosavljevic

IPC分类号： H01L29/775 ,  H01L29/66 ,  G05F3/02 ,  H01L29/786 ,  B82Y10/00 ,  H01L29/06 ,  H01L29/20

CPC分类号： H01L29/0673 ,  B82Y10/00 ,  G05F3/02 ,  H01L21/02603 ,  H01L21/02636 ,  H01L21/225 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/31 ,  H01L21/31116 ,  H01L21/32133 ,  H01L21/324 ,  H01L29/04 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/2003 ,  H01L29/41725 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66462 ,  H01L29/66469 ,  H01L29/775 ,  H01L29/78696

摘要： Transistors suitable for high voltage and high frequency operation. A nanowire is disposed vertically or horizontally on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first semiconductor material, a source region electrically coupled with a first end of the channel region, a drain region electrically coupled with a second end of the channel region, and an extrinsic drain region disposed between the channel region and drain region. The extrinsic drain region has a wider bandgap than that of the first semiconductor. A gate stack including a gate conductor and a gate insulator coaxially wraps completely around the channel region, and drain and source contacts similarly coaxially wrap completely around the drain and source regions.

摘要翻译： 晶体管适用于高电压和高频工作。 纳米线垂直或水平地布置在基底上。 纳米线的纵向长度被限定为第一半导体材料的沟道区域，与沟道区域的第一端电耦合的源极区域，与沟道区域的第二端电耦合的漏极区域和外部漏极 区域设置在沟道区域和漏极区域之间。 外在漏极区具有比第一半导体更宽的带隙。 包括栅极导体和栅极绝缘体的栅极堆叠器完全同轴地包裹在沟道区域周围，并且漏极和源极触点类似地同轴地围绕漏极和源极区域包裹。