公开(公告)号：US5999033A

公开(公告)日：1999-12-07

申请号：US231853

申请日：1999-01-14

申请人： Brent Keeth ,  William K. Waller

发明人： Brent Keeth ,  William K. Waller

IPC分类号： G11C8/08 ,  H03K3/356 ,  H03K19/00 ,  H03K19/0185 ,  H03L5/00

CPC分类号： G11C8/08 ,  H03K19/0013 ,  H03K19/018521 ,  H03K3/356182

摘要： A high speed, low-to-high voltage CMOS driver circuit has a CMOS output stage, an intermediate voltage translation stage, and an input stage. The input and intermediate stages are designed to generate mutually exclusive control signals which activate the PMOS and NMOS transistors of the output stage. The control signals operably turn "off" the active transistor before turning "on" the inactive transistor. Independent control signals substantially reduce or eliminate crossing current in the output stage to thereby reduce energy power waste.

摘要翻译： 高速，低至高电压CMOS驱动电路具有CMOS输出级，中间电压转换级和输入级。 输入和中间级被设计为产生激活输出级的PMOS和NMOS晶体管的互斥控制信号。 控制信号可操作地在有效晶体管“接通”无效晶体管之前关闭有源晶体管。 独立控制信号显着地减少或消除输出级中的交叉电流，从而减少能量浪费。

公开(公告)号：US5901105A

公开(公告)日：1999-05-04

申请号：US869035

申请日：1997-06-05

申请人： Adrian E Ong ,  Paul S. Zagar ,  Troy Manning ,  Brent Keeth ,  Ken Waller

发明人： Adrian E Ong ,  Paul S. Zagar ,  Troy Manning ,  Brent Keeth ,  Ken Waller

IPC分类号： G11C5/02 ,  G11C7/10 ,  G11C11/4096 ,  G11C29/00 ,  G11C29/36 ,  G11C8/00

CPC分类号： G11C29/785 ,  G11C11/4096 ,  G11C29/80 ,  G11C29/88 ,  G11C5/025 ,  G11C7/10 ,  G11C29/36

摘要： A semiconductor dynamic random-access memory (DRAM) device embodying numerous features that collectively and/or individually prove beneficial and advantageous with regard to such considerations as density, power consumption, speed, and redundancy is disclosed. The device is a 64 Mbit DRAM comprising eight substantially identical 8 Mbit partial array blocks (PABs), each pair of PABs comprising a 16 Mbit quadrant of the device. Between the top two quadrants and between the bottom two quadrants are column blocks containing I/O read/write circuitry, column redundancy fuses, and column decode circuitry. Column select lines originate from the column blocks and extend right and left across the width of each quadrant. Each PAB comprises eight substantially identical 1 Mbit sub-array blocks (SABs). Associated with each SAB are a plurality of local row decoder circuits functioning to receive partially decoded row addresses from a column predecoder circuit and generating local row addresses supplied to the SAB with which they are associated. Various pre- and/or post-packaging options are provided for enabling a large degree of versatility, redundancy, and economy of design. Programmable options of the disclosed device are programmable by means of both laser fuses and electrical fuses. In the RAS chain, circuitry is provided for simulating the RC time constant behavior of word lines and digit lines during memory accesses, such that memory access cycle time can be optimized. Test data compression circuitry optimizes the process of testing each cell in the array. On-chip topology circuitry simplifies the testing of the device.

摘要翻译： 公开了一种体现许多特征的半导体动态随机存取存储器（DRAM）装置，它们集中和/或单独地证明了在诸如密度，功耗，速度和冗余度之类的考虑方面是有利和有利的。 该器件是包括八个基本上相同的8兆位部分阵列块（PAB）的64Mbit DRAM，每对PAB包括该器件的16Mb象限。 顶部两个象限之间和底部两个象限之间是包含I / O读/写电路，列冗余保险丝和列解码电路的列块。 列选择线来自列块，并在每个象限的宽度上左右延伸。 每个PAB包括八个基本上相同的1兆位子阵列块（SAB）。 与每个SAB相关联的是多个本地行解码器电路，用于从列预解码器电路接收部分解码的行地址，并产生提供给与它们相关联的SAB的本地行地址。 提供了各种前置和/或后封装选项，以实现大量多功能性，冗余性和设计经济性。 所公开的设备的可编程选项可通过激光熔丝和电熔丝两者来编程。 在RAS链中，提供电路用于在存储器访问期间模拟字线和数字线的RC时间常数行为，使得可以优化存储器访问周期时间。 测试数据压缩电路优化了测试阵列中每个单元的过程。 片上拓扑电路简化了器件的测试。

公开(公告)号：US5872736A

公开(公告)日：1999-02-16

申请号：US738529

申请日：1996-10-28

申请人： Brent Keeth

发明人： Brent Keeth

IPC分类号： G11C11/417 ,  G06F3/00 ,  G06F13/16 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C11/401 ,  G11C11/409 ,  G11C16/06

CPC分类号： G11C7/1093 ,  G11C7/1042 ,  G11C7/1078 ,  G11C7/22

摘要： A data bus is described which has integrated circuits, such as memory circuits, coupled thereto. The integrated circuits include an input buffer circuit adapted to receive and latch high speed data transmissions. The input buffer circuit equilibrates a sensing circuit, samples input data, senses the sampled input data, and latches the sensed data during different phases of an input clock cycle. An input buffer circuit is described which has two receiver circuits for receiving data transmissions having a higher speed data transmissions.

公开(公告)号：US5838150A

公开(公告)日：1998-11-17

申请号：US948386

申请日：1997-10-10

申请人： Brent Keeth

发明人： Brent Keeth

IPC分类号： G05F3/24 ,  G11C5/14 ,  H02N7/219

CPC分类号： G05F3/247 ,  G11C5/147

摘要： A voltage regulator (10) that regulates an input voltage. The voltage regulator (10) includes a current source (20) that generates a reference current. The voltage regulator also includes a voltage translation circuit (30), coupled to and responsive to the current source (20), that increases the input voltage to generate a differential voltage signal. The voltage regulator (10) further includes a differential comparator circuit (40) coupled to the voltage translation circuit (30) that generates a control signal based on the differential voltage from the voltage translation circuit (30) to indicate when the input voltage should be adjusted.

公开(公告)号：US5761145A

公开(公告)日：1998-06-02

申请号：US685783

申请日：1996-07-24

申请人： Paul S. Zagar ,  Brent Keeth ,  Adrian E. Ong

发明人： Paul S. Zagar ,  Brent Keeth ,  Adrian E. Ong

IPC分类号： G06F12/16 ,  G01R31/30 ,  G06F11/22 ,  G11C29/00 ,  G11C29/02 ,  G11C29/04 ,  G11C29/44 ,  G11C29/50 ,  G11C13/00

CPC分类号： G11C29/70 ,  G01R31/3004 ,  G06F11/22 ,  G11C29/02 ,  G11C29/44 ,  G11C29/50 ,  G11C29/83 ,  G11C29/832 ,  G11C29/88 ,  G11C11/401 ,  G11C2029/5006

摘要： An integrated circuit memory device has multiple subarray partitions which can be independently isolated from the remaining circuitry on the integrated circuit. Subarrays of the integrated circuit can be independently tested. Should a subarray of the integrated circuit be found inoperable it is electrically isolated from the remaining circuitry on the integrated circuit so that it cannot interfere with the normal operation of the remaining circuitry. Defects such as power to ground shorts in a subarray which would have previously been catastrophic can be electrically isolated allowing the remaining functional subarrays to be utilized. Integrated circuit repair by isolation of inoperative elements eliminates the current draw and other performance degradations that have previously been associated with integrated circuits with defects repaired through the incorporation of redundant elements alone.

公开(公告)号：US5694035A

公开(公告)日：1997-12-02

申请号：US779478

申请日：1997-01-07

申请人： Brent Keeth

发明人： Brent Keeth

IPC分类号： G05F3/24 ,  G11C5/14 ,  H02N7/219

CPC分类号： G11C5/147 ,  G05F3/24

摘要： A power regulation circuit features an improved regulation circuit for use with a voltage multiplier circuit, such as a Vccp pump for a DRAM. The power regulation circuit includes: a high-gain differential comparator, dual input level translators, and a constant current bias generator. The dual input level translators lower the respective voltage levels of a reference voltage level and the output of the power regulation circuit, which is monitored to provide the desired regulation. The translated input signals are coupled as inputs to the differential comparator. Translation keeps the inputs within the input common mode range of the differential comparator. The differential comparator acts in concert with the constant current bias generator to regulate the output of the power regulation circuit at a constant and steady level. Using current mirrors, the constant current bias generator provides a fixed voltage for ensuring that approximately the same amount of current passes through each of the dual level translators. Feedback is provided from the output of the regulation circuit to the differential comparator to provide the desired level of hysterisis control.

摘要翻译： 功率调节电路具有用于诸如用于DRAM的Vccp泵的电压倍增器电路的改进的调节电路。 功率调节电路包括：高增益差分比较器，双输入电平转换器和恒流偏置发生器。 双输入电平转换器降低参考电压电平的相应电压电平和功率调节电路的输出，其被监视以提供期望的调节。 转换的输入信号作为输入耦合到差分比较器。 转换将输入保持在差分比较器的输入共模范围内。 差分比较器与恒流偏置发生器协调工作，以稳定和稳定的电平调节功率调节电路的输出。 使用电流镜，恒流偏置发生器提供固定电压，以确保大致相同数量的电流通过每个双电平转换器。 从调节电路的输出到差分比较器提供反馈，以提供期望的滞后控制水平。

公开(公告)号：US5668751A

公开(公告)日：1997-09-16

申请号：US690777

申请日：1996-08-01

申请人： Joseph C. Sher ,  Brent Keeth

发明人： Joseph C. Sher ,  Brent Keeth

IPC分类号： G11C17/18 ,  G11C17/00 ,  G11C7/00

CPC分类号： G11C17/18

摘要： A self-timing antifuse programming controller optimizes programming of one or many antifuses. A programming current through the antifuse is monitored until it reaches a current trip point, thereby initiating a delay period. The delay period is determined by charging a capacitor with a scaled replicate of the antifuse current until a trip point voltage is reached. Antifuses which are more resistive receive a longer programming time. The current trip point and delay period are independently programmable. The antifuse programming controller also flags completion of antifuse programming allowing expeditious programming of further antifuses in an array of antifuses to minimize overall programming time.

摘要翻译： 自适应反熔丝编程控制器优化了一个或多个反熔丝的编程。 监控通过反熔丝的编程电流，直至达到当前的跳闸点，从而启动延迟时间。 通过用反熔断电流的缩放复制对电容器充电直到达到跳变点电压来确定延迟时间。 更具阻力的防潮剂可以节省更长的编程时间。 当前的跳闸点和延迟周期可独立编程。 反熔丝编程控制器还标记反熔丝编程的完成，从而可以快速编程反熔丝阵列中的另外的反熔丝，从而最小化总体编程时间。

公开(公告)号：US5627487A

公开(公告)日：1997-05-06

申请号：US495889

申请日：1995-06-28

申请人： Brent Keeth

发明人： Brent Keeth

IPC分类号： H03K19/00 ,  H03K19/003 ,  H03K17/687

CPC分类号： H03K19/0013 ,  H03K19/00361

摘要： A CMOS driver device including an output stage having a first PMOS transistor and an NMOS transistor serially connected between a first voltage and ground and having a second PMOS transistor and the NMOS transistor serially connected between the second voltage and ground. The driver device further includes control logic for mutually exclusively controlling the first PMOS transistor and the second PMOS transistor such that during a first time period an output of the output stage is driven to the first voltage and that during a second subsequent time period the output is driven to the second voltage. The control logic further includes logic for mutually exclusively controlling the first and second PMOS transistors and the NMOS transistor such that prior to enabling one of the first and second PMOS transistors, the NMOS transistor is disabled.

摘要翻译： 一种CMOS驱动器装置，包括具有第一PMOS晶体管和串联连接在第一电压和地之间的NMOS晶体管和具有串联连接在第二电压和地之间的第二PMOS晶体管和NMOS晶体管的输出级。 驱动器装置还包括用于互斥地控制第一PMOS晶体管和第二PMOS晶体管的控制逻辑，使得在第一时间段期间输出级的输出被驱动到第一电压，并且在第二后续时间段期间，输出为 驱动到第二电压。 控制逻辑还包括用于互斥地控制第一和第二PMOS晶体管和NMOS晶体管的逻辑，使得在启用第一和第二PMOS晶体管之一之前，NMOS晶体管被禁止。

公开(公告)号：US5519360A

公开(公告)日：1996-05-21

申请号：US506216

申请日：1995-07-24

申请人： Brent Keeth

发明人： Brent Keeth

IPC分类号： H03K3/03 ,  H03L3/00 ,  H03B5/24

CPC分类号： H03L3/00 ,  H03K3/0315

摘要： An integrated memory circuit is described which includes a charge pump for producing a pumped voltage and a ring oscillator coupled to the charge pump. The ring oscillator is used to operate the charge pump, such that pump cycles are activated on the edges of the oscillator output. The ring oscillator includes an oscillator enable circuit which is controlled by a regulator to maintain a controlled pump voltage. The oscillator enable circuit immediately shuts the ring oscillator off when the pump voltage reaches a pre-determined upper voltage limit so that additional oscillator cycles are eliminated, thereby, reducing the chance of an overshoot in the pump voltage. The oscillator enable circuit turns the oscillator on when the pump voltage decreases to a predetermined lower level.

摘要翻译： 描述了一种集成存储器电路，其包括用于产生泵浦电压的电荷泵和耦合到电荷泵的环形振荡器。 环形振荡器用于操作电荷泵，使得泵浦周期在振荡器输出的边沿被激活。 环形振荡器包括振荡器使能电路，其由调节器控制以维持受控的泵浦电压。 当泵电压达到预定的上限电压时，振荡器使能电路立即关闭环形振荡器，从而消除额外的振荡器周期，从而减少泵电压过冲的机会。 当泵电压降低到预定的较低电平时，振荡器使能电路使振荡器接通。

公开(公告)号：US5508604A

公开(公告)日：1996-04-16

申请号：US372275

申请日：1995-01-11

申请人： Brent Keeth

发明人： Brent Keeth

IPC分类号： G05F3/24

CPC分类号： G05F3/242

摘要： A band gap voltage reference circuit operates between a positive supply voltage and ground. The inputs to a difference amplifier of the band gap reference circuit are biased above the voltage drop of the base-emitter junctions of the band gap reference. The bias voltage is then subtracted from the difference amplifier output by a second difference amplifier. In addition, a bootstrap circuit assures a nonzero output from the first difference amplifier. Other embodiments wherein the band gap reference circuit is more generally a summing circuit are disclosed.

摘要翻译： 带隙电压参考电路在正电源电压和地之间工作。 带隙参考电路的差分放大器的输入偏置在带隙基准的基极 - 发射极结的电压降之上。 然后通过第二差分放大器从差分放大器输出中减去偏置电压。 此外，自举电路确保来自第一差分放大器的非零输出。 公开了其中带隙参考电路更通常为求和电路的其它实施例。