公开(公告)号：US09385054B2

公开(公告)日：2016-07-05

申请号：US14533370

申请日：2014-11-05

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yoshiyuki Kurokawa

IPC: G11C29/00 ,  H01L21/66 ,  G11C5/02 ,  G11C29/18 ,  G11C29/04 ,  G11C29/12 ,  G11C29/44

CPC classification number: H01L22/20 ,  G11C5/02 ,  G11C29/04 ,  G11C29/18 ,  G11C29/78 ,  G11C29/785 ,  G11C29/82 ,  G11C2029/1204 ,  G11C2029/1802 ,  G11C2029/4402

Abstract: A method by which a defective memory cell can be efficiently excluded from a memory cell array is provided. In one embodiment, the memory cell array includes M word lines and (N+K) bit lines. K of the bit lines are spares (i.e., redundant bit lines). Programmable switches in a switch array are programmed so that the switch array connects a driver that drives the bit lines to N bit lines that are not connected to defective memory cells. The memory cell array is tested by a test circuit connected to the bit lines in such a manner that the test circuit transmits and receives a signal to and from the bit lines via the switch array. The test circuit may be formed using a reconfigurable circuit. Other embodiments may be claimed.

Abstract translation: 提供了可以有效地从存储单元阵列中排除有缺陷的存储单元的方法。 在一个实施例中，存储单元阵列包括M个字线和（N + K个）位线。 位线的K是备用（即冗余位线）。 开关阵列中的可编程开关被编程，使得开关阵列将驱动位线的驱动器连接到不连接到有缺陷的存储单元的N位线。 存储单元阵列通过连接到位线的测试电路以测试电路经由开关阵列向位线和从位线接收信号的方式进行测试。 可以使用可重构电路来形成测试电路。 可以要求保护其他实施例。

公开(公告)号：US09362984B2

公开(公告)日：2016-06-07

申请号：US13785359

申请日：2013-03-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshiyuki Kurokawa

IPC: H01F27/42 ,  H01F38/00 ,  H01F37/00 ,  H04B5/00 ,  G06F15/78

CPC classification number: H04B5/0037 ,  G06F15/7832 ,  Y02D10/12 ,  Y02D10/13

Abstract: In a multi-core semiconductor device, a data bus between CPUs or the like consumes a larger amount of power. By provision of a plurality of CPUs which transmit data by a backscattering method of a wireless signal, a router circuit which mediates data transmission and reception between the CPUs or the like, and a thread control circuit which has a thread scheduling function, a semiconductor device which consumes less power and has high arithmetic performance can be provided at low cost.

公开(公告)号：US09324747B2

公开(公告)日：2016-04-26

申请号：US14641625

申请日：2015-03-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Masayuki Sakakura ,  Yoshiyuki Kurokawa

IPC: H01L29/10 ,  H01L27/146

CPC classification number: H01L27/14616 ,  H01L27/14607 ,  H01L27/14609 ,  H01L27/14612 ,  H01L27/14641 ,  H01L27/14643 ,  H01L27/14689

Abstract: An imaging device is provided at a lower manufacturing cost. In a light-receiving portion of an imaging device which includes the light-receiving portion, a first transistor connected to the light-receiving portion, and a peripheral circuit, a comb-like n-type semiconductor and a comb-like p-type semiconductor are arranged so as to engage with each other in a plan view. Further, the light-receiving portion and the first transistor overlap with each other. The peripheral circuit includes a second transistor and a third transistor. Further, the second transistor and the third transistor include semiconductor layers having different bandgaps. Further, one of the semiconductor layers of the second transistor and the third transistor has the same bandgap as a semiconductor layer of the first transistor.

Abstract translation: 以较低的制造成本提供成像装置。 在包括光接收部分的成像装置的光接收部分中，连接到光接收部分的第一晶体管，外围电路，梳状n型半导体和梳状p型 半导体布置成在平面图中彼此接合。 此外，光接收部分和第一晶体管彼此重叠。 外围电路包括第二晶体管和第三晶体管。 此外，第二晶体管和第三晶体管包括具有不同带隙的半导体层。 此外，第二晶体管和第三晶体管的半导体层之一具有与第一晶体管的半导体层相同的带隙。

公开(公告)号：US09305612B2

公开(公告)日：2016-04-05

申请号：US14493737

申请日：2014-09-23

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshiyuki Kurokawa

IPC: G11C5/06 ,  G11C7/00 ,  G11C7/10 ,  G11C11/405 ,  G11C11/4072 ,  H03K19/177 ,  G11C11/401

CPC classification number: G11C7/00 ,  G11C5/06 ,  G11C7/1006 ,  G11C11/401 ,  G11C11/405 ,  G11C11/4072 ,  H03K19/1778

Abstract: A low-power programmable LSI that can perform configuration (dynamic configuration) at high speed and can quickly start is provided. The programmable LSI includes a plurality of logic elements and a memory element for storing configuration data to be input to the plurality of logic elements. The plurality of logic elements each include a configuration memory. Each of the plurality of logic elements performs different arithmetic processing and changes an electrical connection between the logic elements in accordance with the configuration data stored in the configuration memory. The memory element is formed using a storage element including a transistor whose channel is formed in an oxide semiconductor layer and a node set in a floating state when the transistor is turned off.

Abstract translation: 提供可以高速执行配置（动态配置）并可快速启动的低功耗可编程LSI。 可编程LSI包括多个逻辑元件和用于存储要输入到多个逻辑元件的配置数据的存储元件。 多个逻辑元件各自包括配置存储器。 多个逻辑元件中的每一个执行不同的运算处理，并且根据存储在配置存储器中的配置数据改变逻辑元件之间的电连接。 存储元件使用包括其沟道形成在氧化物半导体层中的晶体管的存储元件和当晶体管截止时设置为浮置状态的节点。

公开(公告)号：US09196648B2

公开(公告)日：2015-11-24

申请号：US14253132

申请日：2014-04-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Munehiro Kozuma ,  Yoshiyuki Kurokawa

IPC: H01L27/146

CPC classification number: H01L27/14643 ,  H01L27/14603 ,  H01L27/14607 ,  H01L27/14609

Abstract: An object of the invention is to improve the accuracy of light detection in a photosensor, and to increase the light-receiving area of the photosensor. The photosensor includes: a light-receiving element which converts light into an electric signal; a first transistor which transfers the electric signal; and a second transistor which amplifies the electric signal. The light-receiving element includes a silicon semiconductor, and the first transistor includes an oxide semiconductor. The light-receiving element is a lateral junction photodiode, and an n-region or a p-region included in the light-receiving element overlaps with the first transistor.

Abstract translation: 本发明的目的是提高光传感器中光检测的精度，并增加光传感器的光接收面积。 光传感器包括：将光转换成电信号的光接收元件; 传输电信号的第一晶体管; 以及放大电信号的第二晶体管。 光接收元件包括硅半导体，并且第一晶体管包括氧化物半导体。 光接收元件是横向结光电二极管，并且包含在光接收元件中的n区域或p区域与第一晶体管重叠。

公开(公告)号：US09093136B2

公开(公告)日：2015-07-28

申请号：US14227190

申请日：2014-03-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshiyuki Kurokawa

IPC: G11C11/34 ,  G11C5/14 ,  G11C11/405 ,  H01L27/115 ,  H01L27/12 ,  G11C11/40 ,  G11C16/04

CPC classification number: G11C5/14 ,  G11C11/40 ,  G11C11/405 ,  G11C16/0433 ,  H01L27/1156 ,  H01L27/1225

Abstract: It is an object to provide a signal processing circuit for which a complex manufacturing process is not necessary and whose power consumption can be suppressed. In particular, it is an object to provide a signal processing circuit whose power consumption can be suppressed by stopping the power supply for a short time. The signal processing circuit includes a control circuit, an arithmetic unit, and a buffer memory device. The buffer memory device stores data sent from the main memory device or the arithmetic unit in accordance with an instruction from the control unit; the buffer memory device comprises a plurality of memory cells; and the memory cells each include a transistor including an oxide semiconductor in a channel formation region and a memory element to which charge whose amount depends on a value of the data is supplied via the transistor.

Abstract translation: 本发明的目的是提供一种不需要复杂制造处理并且可以抑制其功耗的信号处理电路。 特别地，本发明的目的是提供一种通过在短时间内停止供电来抑制功耗的信号处理电路。 信号处理电路包括控制电路，运算单元和缓冲存储器件。 缓冲存储器装置根据来自控制单元的指令存储从主存储器件或算术单元发送的数据; 缓冲存储器件包括多个存储器单元; 并且存储单元各自包括在通道形成区域中包括氧化物半导体的晶体管和经由晶体管提供其依赖于数据值的电荷的存储元件。

公开(公告)号：US09007092B2

公开(公告)日：2015-04-14

申请号：US14217628

申请日：2014-03-18

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Munehiro Kozuma ,  Yoshiyuki Kurokawa

IPC: H03K19/00

CPC classification number: H03K19/0013

Abstract: To provide a charge pump circuit to manufacture a low-power-consumption PLD. A semiconductor device includes a first circuit and a second circuit electrically connected to the first circuit. A charge pump circuit formed of a transistor including an oxide semiconductor and a boosting control circuit controlling the charge pump circuit are provided between the first circuit and the second circuit. The first circuit and the charge pump circuit operate at first power supply voltage, and the boosting control circuit and the second circuit operate at second power supply voltage. The first power supply voltage is lower than the second power supply voltage.

Abstract translation: 提供电荷泵电路来制造低功耗PLD。 半导体器件包括电连接到第一电路的第一电路和第二电路。 在第一电路和第二电路之间设置由包括氧化物半导体的晶体管和控制电荷泵电路的升压控制电路构成的电荷泵电路。 第一电路和电荷泵电路在第一电源电压下工作，并且升压控制电路和第二电路在第二电源电压下工作。 第一电源电压低于第二电源电压。

公开(公告)号：US08952722B2

公开(公告)日：2015-02-10

申请号：US14051782

申请日：2013-10-11

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takayuki Ikeda ,  Yoshiyuki Kurokawa

IPC: G06F7/38 ,  H03K19/173 ,  H03K19/00 ,  H03K19/177

CPC classification number: H03K19/0008 ,  H03K19/17748 ,  H03K19/1776 ,  H03K19/17772

Abstract: Configuration is performed in accordance with a plurality of states when power supply voltage is supplied intermittently. At the time of start of supply of power supply voltage with configuration, a programmable logic device is sequentially changed into a first state where configuration data is not set in a configuration memory, a second state where the configuration memory is initialized, and a third state where the configuration data can be set in the configuration memory. At the time of start of supply of power supply voltage without configuration, the programmable logic device is sequentially changed into a fourth state where the configuration data is not set in the configuration memory and the third state. The first to fourth states are switched to any one of the states by control of a first state signal and a second state signal.

Abstract translation: 当间歇地供给电源电压时，根据多个状态执行配置。 在通过配置开始供电电源时，可编程逻辑器件被顺序地改变为配置数据未被设置在配置存储器中的第一状态，配置存储器被初始化的第二状态和第三状态 其中配置数据可以在配置存储器中设置。 在没有配置的电源电压开始供电时，可编程逻辑器件被顺序地改变为配置数据未被配置在配置存储器和第三状态中的第四状态。 通过控制第一状态信号和第二状态信号，将第一至第四状态切换到任一状态。

公开(公告)号：US08945962B2

公开(公告)日：2015-02-03

申请号：US13845443

申请日：2013-03-18

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Yoshiyuki Kurokawa ,  Yasuhiro Jinbo ,  Satoshi Kobayashi ,  Daisuke Kawae

IPC: H01L21/00 ,  H01L29/66 ,  H01L29/04 ,  H01L29/786 ,  H01L49/02 ,  H01L29/417 ,  H01L29/49

CPC classification number: H01L29/66765 ,  H01L28/40 ,  H01L29/04 ,  H01L29/41733 ,  H01L29/4908 ,  H01L29/78696

Abstract: In a method for manufacturing a semiconductor device including a transistor and a conductive film over a substrate, a first insulating film and a second insulating film are formed over the transistor and the conductive film sequentially. Then, an opening and a recessed portion are formed in the second insulating film using one multi-tone photomask, wherein the opening is deeper than the recessed portion in the second insulating film. By using the opening, a first contact hole exposing one of the electrodes of the transistor is formed through the first and second insulating films and, by using the recessed portion, a second contact hole exposing the first insulating film is formed through the second insulating film. Moreover, an electrode is formed on and in contact with the one of the electrodes in the first contact hole and the first insulating film in the second contact hole.

Abstract translation: 在衬底上制造包括晶体管和导电膜的半导体器件的方法中，依次在晶体管和导电膜上形成第一绝缘膜和第二绝缘膜。 然后，使用一个多色光掩模在第二绝缘膜中形成开口和凹部，其中开口比第二绝缘膜中的凹部更深。 通过使用开口，通过第一和第二绝缘膜形成暴露晶体管的一个电极的第一接触孔，并且通过使用凹部，暴露第一绝缘膜的第二接触孔通过第二绝缘膜形成 。 此外，在第一接触孔中的一个电极和第二接触孔中的第一绝缘膜上形成电极并与其接触。

公开(公告)号：US20150001529A1

公开(公告)日：2015-01-01

申请号：US14310096

申请日：2014-06-20

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yoshiyuki Kurokawa

IPC: H01L29/786 ,  H01L27/12

CPC classification number: H01L27/1229 ,  H01L27/1156 ,  H01L27/1225

Abstract: A storage device with long data retention time is configured to include a first transistor, a second transistor, and a third transistor. The first transistor controls electrical connection between a first wiring and a gate of the second transistor. The second transistor controls electrical connection between a second wiring and a gate of the third transistor. The off-state current of the first transistor is lower than that of the third transistor. The leakage current of the second transistor is lower than that of the third transistor.

Abstract translation: 具有长数据保持时间的存储设备被配置为包括第一晶体管，第二晶体管和第三晶体管。 第一晶体管控制第一布线和第二晶体管的栅极之间的电连接。 第二晶体管控制第二布线和第三晶体管的栅极之间的电连接。 第一晶体管的截止电流低于第三晶体管的截止电流。 第二晶体管的漏电流低于第三晶体管的漏电流。