公开(公告)号：US20160343717A1

公开(公告)日：2016-11-24

申请号：US15229709

申请日：2016-08-05

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Marc Battista ,  François Tailliet

IPC: H01L27/11 ,  G11C16/08 ,  H01L29/51 ,  H01L21/8234 ,  H01L29/49 ,  G11C14/00 ,  G11C11/418

CPC classification number: H01L27/1104 ,  G11C11/4125 ,  G11C11/418 ,  G11C14/0063 ,  G11C16/045 ,  G11C16/08 ,  H01L21/823462 ,  H01L27/088 ,  H01L29/4916 ,  H01L29/513

Abstract: An integrated structure includes a first MOS transistor with a first controllable gate region overlying a first gate dielectric and a second MOS transistor neighboring the first MOS transistor and having a second controllable gate region overlying the first gate dielectric. A common conductive region overlies the first and second gate regions and is separated therefrom by a second gate dielectric. The common conductive region includes a continuous element located over a portion of the first and second gate regions and a branch extending downward from the continuous element toward the substrate as far as the first gate dielectric. The branch located between the first and second gate regions.

公开(公告)号：US09455034B1

公开(公告)日：2016-09-27

申请号：US15055552

申请日：2016-02-27

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Marc Battista

IPC: G11C16/06 ,  G11C13/00 ,  G11C16/34

CPC classification number: G11C16/10 ,  G11C16/08 ,  G11C16/14 ,  G11C16/30 ,  G11C16/32 ,  G11C16/3436 ,  G11C16/3445 ,  G11C16/3459

Abstract: An operation for writing at least one datum in at least one memory cell of the electrically erasable and programmable read-only memory type comprises at least one step of erasing or of programming of the cell by a corresponding erasing or programming pulse. The correct or incorrect conducting of the writing operation is checked by an analysis of the form of the erasing or programming pulse during the corresponding erasing or programming step. The result of this analysis is representative of the writing operation being conducted correctly or incorrectly.

Abstract translation: 用于在电可擦除和可编程只读存储器类型的至少一个存储单元中写入至少一个数据的操作包括通过相应的擦除或编程脉冲擦除或编程单元的至少一个步骤。 通过在相应的擦除或编程步骤期间对擦除或编程脉冲的形式的分析来检查写入操作的正确或不正确的导通。 该分析的结果代表正在进行的写入操作正确或不正确。

公开(公告)号：US09431108B2

公开(公告)日：2016-08-30

申请号：US14657963

申请日：2015-03-13

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Marc Battista ,  François Tailliet

IPC: H01L29/49 ,  G11C16/04 ,  G11C11/412 ,  H01L27/11 ,  G11C11/418 ,  G11C16/08 ,  H01L27/088 ,  H01L29/51

CPC classification number: H01L27/1104 ,  G11C11/4125 ,  G11C11/418 ,  G11C14/0063 ,  G11C16/045 ,  G11C16/08 ,  H01L21/823462 ,  H01L27/088 ,  H01L29/4916 ,  H01L29/513

Abstract: An integrated structure includes a first MOS transistor with a first controllable gate region overlying a first gate dielectric and a second MOS transistor neighboring the first MOS transistor and having a second controllable gate region overlying the first gate dielectric. A common conductive region overlies the first and second gate regions and is separated therefrom by a second gate dielectric. The common conductive region includes a continuous element located over a portion of the first and second gate regions and a branch extending downward from the continuous element toward the substrate as far as the first gate dielectric. The branch located between the first and second gate regions.

Abstract translation: 集成结构包括具有覆盖第一栅极电介质的第一可控栅极区域和与第一MOS晶体管相邻并具有覆盖第一栅极电介质的第二可控栅极区域的第一MOS晶体管的第一MOS晶体管。 公共导电区域覆盖第一和第二栅极区域并且由第二栅极电介质分离。 公共导电区域包括位于第一和第二栅极区域的一部分上的连续元件以及从连续元件向衬底延伸至第一栅极电介质的分支。 位于第一和第二栅极区之间的分支。

公开(公告)号：US20160148697A1

公开(公告)日：2016-05-26

申请号：US14849257

申请日：2015-09-09

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Marc Battista

IPC: G11C16/14 ,  G11C16/08

CPC classification number: G11C16/14 ,  G11C5/025 ,  G11C8/08 ,  G11C8/10 ,  G11C8/12 ,  G11C8/14 ,  G11C16/0433 ,  G11C16/08

Abstract: A non-volatile memory device includes a matrix memory plane with columns of memory words respectively formed on each row of the memory plane by groups of memory cells and control elements respectively associated with the memory words of each row. At least some of the control elements associated with the memory words of the corresponding row form at least one control block of B control elements disposed next to one another, adjacent to a memory block containing the B memory words disposed next to one another and associated with these B control elements, a first electrically-conducting link connecting one of the B control elements to all the control electrodes of the state transistors of the corresponding group of memory cells and B-1 second electrically-conducting link(s) respectively connecting the B-1 control element(s) to all the control electrodes of the state transistors of the B-1 corresponding group(s) of memory cells.

Abstract translation: 非易失性存储器件包括矩阵存储器平面，其中存储器列的列分别在存储器平面的每一行上由存储器单元组和分别与每行的存储器字相关联的控制元件组组成。 与相应行的存储器字相关联的至少一些控制元件形成彼此相邻布置的B个控制元件的至少一个控制块，与包含彼此相邻布置的B存储器字的存储块相邻， 这些B控制元件，将B个控制元件中的一个连接到相应组的存储单元的状态晶体管的所有控制电极的第一导电链路和分别连接B的B-1个第二导电链路 -1个控制元件连接到存储器单元的B-1个相应组的状态晶体管的所有控制电极。

公开(公告)号：US20140369120A1

公开(公告)日：2014-12-18

申请号：US14298264

申请日：2014-06-06

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Marc Battista

IPC: G11C14/00

CPC classification number: G11C14/0063 ,  G11C16/10

Abstract: A memory device includes at least one memory cell having a first SRAM-type elementary memory cell having two inverters coupled to one another crosswise and two groups, each having at least one non-volatile elementary memory cell. The non-volatile elementary memory cells of the two groups are coupled firstly to a supply terminal and secondly to the outputs and to the inputs of the two inverters via a controllable interconnection stage.

Abstract translation: 存储器件包括至少一个具有第一SRAM型元件存储器单元的存储器单元，所述第一SRAM型元件存储器单元具有彼此交叉耦合的两个反相器和两组，每个具有至少一个非易失性基本存储器单元。 两组的非易失性基本存储单元首先通过可控制的互连级耦合到电源端子，其次耦合到两个反相器的输出端和输入端。

公开(公告)号：US20140369119A1

公开(公告)日：2014-12-18

申请号：US14296014

申请日：2014-06-04

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： François Tailliet ,  Marc Battista

IPC: G11C16/04 ,  G11C14/00 ,  G11C16/20

CPC classification number: G11C16/0408 ,  G11C11/404 ,  G11C14/0018 ,  G11C14/0063 ,  G11C16/20

Abstract: A memory device includes a memory cell with an elementary SRAM-type cell and an elementary module coupled between a supply terminal and the elementary SRAM-type cell. The elementary module has a single nonvolatile EEPROM elementary memory cell that includes a floating gate transistor. The elementary module also has a controllable interconnection stage that can be controlled by a control signal external to the memory cell. The nonvolatile elementary memory cell and the controllable interconnection stage are connected to one another. The floating gate transistor of the nonvolatile memory cell is controllable to be turned off when a data item stored in the elementary SRAM-type cell is programmed into the nonvolatile elementary cell.

Abstract translation: 存储器件包括具有基本SRAM型单元的存储单元和耦合在供电端和基本SRAM型单元之间的基本模块。 基本模块具有包括浮栅晶体管的单个非易失性EEPROM单元存储单元。 基本模块还具有可控制的互连级，其可以由存储器单元外部的控制信号控制。 非易失性基本存储单元和可控互连级彼此连接。 当存储在基本SRAM型单元中的数据项被编程到非易失性单元中时，非易失性存储单元的浮置栅晶体管被控制为截止。

公开(公告)号：US08884689B2

公开(公告)日：2014-11-11

申请号：US13868866

申请日：2013-04-23

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francois Tailliet ,  Marc Battista

IPC: H03B1/00 ,  H03K5/1252 ,  H03K5/13 ,  H03H11/04 ,  H03K5/00

CPC classification number: H03H11/04 ,  H03K5/1252 ,  H03K5/13 ,  H03K2005/00156

Abstract: A low pass filter comprises a filter input node configured to receive a first logic signal, a filter output node configured to supply a second logic signal, a resistive element comprising a first terminal coupled to the input node and a second terminal coupled to the output node, and a capacitive element comprising a first terminal coupled to the output node and a second terminal. The filter further comprises an inverting gate having a first terminal coupled to the input node and a second terminal coupled to the second terminal of the capacitive element.

Abstract translation: 低通滤波器包括被配置为接收第一逻辑信号的滤波器输入节点，被配置为提供第二逻辑信号的滤波器输出节点，包括耦合到输入节点的第一终端的电阻元件和耦合到输出节点的第二终端 以及电容元件，包括耦合到所述输出节点的第一端子和第二端子。 滤波器还包括反相门，其具有耦合到输入节点的第一端子和耦合到电容元件的第二端子的第二端子。