公开(公告)号：US09472559B2

公开(公告)日：2016-10-18

申请号：US12976340

申请日：2010-12-22

申请人： Yutaka Shionoiri ,  Hiroyuki Miyake ,  Kiyoshi Kato

发明人： Yutaka Shionoiri ,  Hiroyuki Miyake ,  Kiyoshi Kato

IPC分类号： H01L29/10 ,  H01L29/12 ,  H01L27/115 ,  H01L27/12 ,  H01L27/13 ,  G11C16/04

CPC分类号： H01L27/1052 ,  G11C16/0433 ,  H01L27/115 ,  H01L27/1156 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1251 ,  H01L27/1255 ,  H01L27/13 ,  H01L29/78648 ,  H01L29/7869

摘要： It is an object to provide a memory device whose power consumption can be suppressed and a semiconductor device including the memory device. As a switching element for holding electric charge accumulated in a transistor which functions as a memory element, a transistor including an oxide semiconductor film as an active layer is provided for each memory cell in the memory device. The transistor which is used as a memory element has a first gate electrode, a second gate electrode, a semiconductor film located between the first gate electrode and the second gate electrode, a first insulating film located between the first gate electrode and the semiconductor film, a second insulating film located between the second gate electrode and the semiconductor film, and a source electrode and a drain electrode in contact with the semiconductor film.

摘要翻译： 本发明的目的是提供一种能够抑制功耗的存储器件和包括存储器件的半导体器件。 作为用作保持蓄积在用作存储元件的晶体管中的电荷的开关元件，为存储器件中的每个存储单元提供包括氧化物半导体膜作为有源层的晶体管。 用作存储元件的晶体管具有第一栅电极，第二栅电极，位于第一栅电极和第二栅电极之间的半导体膜，位于第一栅电极和半导体膜之间的第一绝缘膜， 位于第二栅电极和半导体膜之间的第二绝缘膜，以及与半导体膜接触的源电极和漏电极。

公开(公告)号：US09057758B2

公开(公告)日：2015-06-16

申请号：US12967230

申请日：2010-12-14

申请人： Kiyoshi Kato ,  Yusuke Sekine ,  Yutaka Shionoiri

发明人： Kiyoshi Kato ,  Yusuke Sekine ,  Yutaka Shionoiri

IPC分类号： G01R31/02 ,  G01R31/27 ,  G01R19/00 ,  G01R31/28 ,  G09G3/20

CPC分类号： G01R31/275 ,  G01R19/0092 ,  G01R31/2884 ,  G09G3/20 ,  G09G2320/029

摘要： An object is to provide a current measurement method which enables a minute current to be measured. To achieve this, the value of a current flowing through an electrical element is not directly measured, but is calculated from a change in potential observed in a predetermined period. The detection of a minute current can be achieved by a measurement method including the steps of applying a predetermined potential to a first terminal of an electrical element comprising the first terminal and a second terminal; measuring an amount of change in potential of a node connected to the second terminal; and calculating, from the amount of change in potential, a value of a current flowing between the first terminal and the second terminal of the electrical element.

摘要翻译： 目的在于提供能够测量微小电流的电流测量方法。 为了实现这一点，不直接测量流过电气元件的电流的值，而是根据在预定周期内观察到的电位变化来计算。 可以通过测量方法来实现微小电流的检测，包括以下步骤：将预定电位施加到包括第一端子和第二端子的电气元件的第一端子; 测量连接到第二终端的节点的电位变化量; 以及根据电位变化量计算在电气元件的第一端子和第二端子之间流动的电流的值。

公开(公告)号：US08552712B2

公开(公告)日：2013-10-08

申请号：US13085606

申请日：2011-04-13

申请人： Kiyoshi Kato ,  Yusuke Sekine ,  Yutaka Shionoiri ,  Kazuma Furutani

发明人： Kiyoshi Kato ,  Yusuke Sekine ,  Yutaka Shionoiri ,  Kazuma Furutani

IPC分类号： G01R19/00 ,  G01R13/04

CPC分类号： G01R31/2601 ,  G01R19/0092

摘要： One object is to provide a method for measuring current by which minute current can be measured. A value of current flowing through an electrical element is not directly measured but is calculated from change in a potential observed in a predetermined period. The method for measuring current includes the steps of: applying a predetermined potential to a first terminal of an electrical element having the first terminal and a second terminal; measuring an amount of change in a potential of a node connected to the second terminal; and calculating, from the amount of change in the potential, a value of current flowing between the first terminal and the second terminal of the electrical element. Thus, the value of minute current can be measured.

摘要翻译： 一个目的是提供一种用于测量可以测量微小电流的电流的方法。 流过电气元件的电流的值不是直接测量的，而是根据在预定周期内观察到的电位的变化计算出的。 用于测量电流的方法包括以下步骤：将预定电位施加到具有第一端子和第二端子的电气元件的第一端子; 测量连接到第二终端的节点的电位变化量; 以及根据所述电位变化量计算在所述电气元件的所述第一端子和所述第二端子之间流动的电流值。 因此，可以测量微小电流的值。

公开(公告)号：US08149018B2

公开(公告)日：2012-04-03

申请号：US12940069

申请日：2010-11-05

申请人： Yutaka Shionoiri ,  Kiyoshi Kato ,  Munehiro Azami

发明人： Yutaka Shionoiri ,  Kiyoshi Kato ,  Munehiro Azami

IPC分类号： G01R19/00

CPC分类号： H03F3/45179 ,  G01R19/00 ,  G11C7/062 ,  G11C11/4091 ,  G11C11/413 ,  G11C2207/063 ,  H03F3/45183 ,  H03F3/45188 ,  H03F2203/45396 ,  H03F2203/45506 ,  H03F2203/45546 ,  H03F2203/45551 ,  H03F2203/45702 ,  H03F2203/45726

摘要： A sense amplifier according to the present invention for detecting a potential difference of signals input to a first input terminal and a second input terminal, includes a first means for applying voltages corresponding to threshold voltages of first and second transistors to gate-source voltages of the first and second transistors, and a second means for transferring signals input to the first and second input terminals to gates of the first and second transistors. In this case, a threshold variation of the first and second transistors is corrected.

公开(公告)号：US20110111721A1

公开(公告)日：2011-05-12

申请号：US13010209

申请日：2011-01-20

申请人： Kiyoshi Kato ,  Yutaka Shionoiri

发明人： Kiyoshi Kato ,  Yutaka Shionoiri

IPC分类号： H04B1/16 ,  H04B7/00

CPC分类号： G06K19/07749 ,  H01L27/1214 ,  H01L27/1266 ,  H01L27/13

摘要： The invention provides a semiconductor device with high yield by reducing an effect of variations in characteristics of a semiconductor element. Further, by reducing an effect of variations in characteristics of a semiconductor element to improve productivity, an inexpensive semiconductor device can be provided. Further, an inexpensive semiconductor device can be provided by forming a semiconductor device in a large amount over a large substrate such as a glass substrate and a flexible substrate. A semiconductor device of the invention includes a demodulation signal generating circuit and an antenna or a wire for connecting the antenna. The demodulation signal generating circuit includes a demodulation circuit and a correction circuit. The correction circuit corrects a first demodulation signal generated from the demodulation circuit and generates a second demodulation signal.

摘要翻译： 本发明通过减少半导体元件的特性变化的影响来提供高产率的半导体器件。 此外，通过减少半导体元件的特性变化的影响以提高生产率，可以提供便宜的半导体器件。 此外，通过在诸如玻璃基板和柔性基板的大基板上大量地形成半导体器件，可以提供廉价的半导体器件。 本发明的半导体器件包括解调信号发生电路和用于连接天线的天线或导线。 解调信号发生电路包括解调电路和校正电路。 校正电路校正从解调电路产生的第一解调信号，并产生第二解调信号。

公开(公告)号：US07876859B2

公开(公告)日：2011-01-25

申请号：US12821588

申请日：2010-06-23

申请人： Kiyoshi Kato ,  Yutaka Shionoiri

发明人： Kiyoshi Kato ,  Yutaka Shionoiri

IPC分类号： H03K9/00 ,  G06K19/06

CPC分类号： G06K19/07749 ,  H01L27/1214 ,  H01L27/1266 ,  H01L27/13

摘要： The invention provides a semiconductor device with high yield by reducing an effect of variations in characteristics of a semiconductor element. Further, by reducing an effect of variations in characteristics of a semiconductor element to improve productivity, an inexpensive semiconductor device can be provided. Further, an inexpensive semiconductor device can be provided by forming a semiconductor device in a large amount over a large substrate such as a glass substrate and a flexible substrate. A semiconductor device of the invention includes a demodulation signal generating circuit and an antenna or a wire for connecting the antenna. The demodulation signal generating circuit includes a demodulation circuit and a correction circuit. The correction circuit corrects a first demodulation signal generated from the demodulation circuit and generates a second demodulation signal.

摘要翻译： 本发明通过减少半导体元件的特性变化的影响来提供高产率的半导体器件。 此外，通过减少半导体元件的特性变化的影响以提高生产率，可以提供便宜的半导体器件。 此外，通过在诸如玻璃基板和柔性基板的大基板上大量地形成半导体器件，可以提供廉价的半导体器件。 本发明的半导体器件包括解调信号发生电路和用于连接天线的天线或导线。 解调信号发生电路包括解调电路和校正电路。 校正电路校正从解调电路产生的第一解调信号，并产生第二解调信号。

公开(公告)号：US07430146B2

公开(公告)日：2008-09-30

申请号：US11554128

申请日：2006-10-30

申请人： Yutaka Shionoiri ,  Tomoaki Atsumi ,  Kiyoshi Kato

发明人： Yutaka Shionoiri ,  Tomoaki Atsumi ,  Kiyoshi Kato

IPC分类号： G11C7/00

CPC分类号： G11C7/12 ,  G11C7/22

摘要： The semiconductor device in which reading and writing of data can be accurately performed by preventing malfunction even when a selection of address delays. The semiconductor device has three factors of a data holding unit, a precharge unit and a delay unit. The data holding unit includes a plurality of memory cells. The precharge unit includes a precharge potential line, a precharge signal line and a plurality of switches. The delay unit includes a plurality of transistors. In addition, it has one or both of an address selecting unit having a column-decoder and a row-decoder and a display unit having a plurality of pixels, as well as the three factors.

摘要翻译： 即使在选择地址延迟的情况下，也可以通过防止故障来准确地执行数据的读取和写入的半导体装置。 半导体器件具有数据保持单元，预充电单元和延迟单元的三个因素。 数据保持单元包括多个存储单元。 预充电单元包括预充电电位线，预充电信号线和多个开关。 延迟单元包括多个晶体管。 此外，它具有地址选择单元，其具有列解码器和行解码器以及具有多个像素的显示单元以及三个因素中的一个或两个。

公开(公告)号：US20070228371A1

公开(公告)日：2007-10-04

申请号：US11758066

申请日：2007-06-05

申请人： Etsuko Asano ,  Kiyoshi Kato ,  Yutaka Shionoiri ,  Masahiko Hayakawa

发明人： Etsuko Asano ,  Kiyoshi Kato ,  Yutaka Shionoiri ,  Masahiko Hayakawa

IPC分类号： H01L23/58

CPC分类号： G01R31/3187 ,  G01R31/31723 ,  G01R31/31725 ,  G01R31/31726

摘要： The present invention provides a method for evaluating an intended element or a parameter. In addition, the invention provides an evaluation method for obtaining a more precise result rapidly. According to the invention, a plurality of evaluation circuits are formed over the same substrate, and while simultaneously operating the plurality of evaluation circuits, an output of one evaluation circuit selected by a selection circuit that is formed over the substrate is arbitrarily evaluated.

摘要翻译： 本发明提供了一种用于评估预期元素或参数的方法。 此外，本发明提供了一种快速获得更精确结果的评估方法。 根据本发明，在相同的基板上形成多个评估电路，并且在同时操作多个评估电路的同时，任意地评估由形成在基板上的选择电路选择的一个评估电路的输出。

公开(公告)号：US20070210364A1

公开(公告)日：2007-09-13

申请号：US11547904

申请日：2005-04-21

申请人： Kiyoshi Kato ,  Yutaka Shionoiri

发明人： Kiyoshi Kato ,  Yutaka Shionoiri

IPC分类号： H01L27/108

CPC分类号： H01L27/1266 ,  G02F1/136213 ,  H01L21/288 ,  H01L21/32051 ,  H01L21/76801 ,  H01L21/76829 ,  H01L21/76838 ,  H01L27/0811 ,  H01L27/10805 ,  H01L27/1214 ,  H01L27/13 ,  H01L29/04 ,  H01L29/78675

摘要： A capacitor capable of functioning as a capacitor even when an AC voltage is applied thereto is provided without increasing the manufacturing steps of a semiconductor device. A transistor is used as a MOS capacitor where a pair of impurity regions formed on opposite sides of a channel formation region are each doped with impurities of different conductivity so as to be used as a source region or a drain region. Specifically, assuming that an impurity region that is doped with N-type impurities is referred to as an N-type region while an impurity region that is doped with P-type impurities is referred to as a P-type region, a transistor is provided where a channel formation region is interposed between the N-type region and the P-type region, which is used as a MOS capacitor.

摘要翻译： 在不增加半导体器件的制造步骤的情况下，即使在施加交流电压的情况下，也可以提供能够作为电容器起作用的电容器。 晶体管用作MOS电容器，其中形成在沟道形成区域的相对侧上的一对杂质区域各自掺杂有不同导电性的杂质，以便用作源极区域或漏极区域。 具体地说，假定掺杂有N型杂质的杂质区域称为N型区域，而掺杂有P型杂质的杂质区域称为P型区域，则提供晶体管 其中沟道形成区域被插入在用作MOS电容器的N型区域和P型区域之间。

公开(公告)号：US20070076515A1

公开(公告)日：2007-04-05

申请号：US11607053

申请日：2006-12-01

申请人： Yutaka Shionoiri ,  Tomoaki Atsumi ,  Kiyoshi Kato

发明人： Yutaka Shionoiri ,  Tomoaki Atsumi ,  Kiyoshi Kato

IPC分类号： G11C8/00

CPC分类号： G11C7/1096 ,  G11C7/1078 ,  G11C7/12 ,  G11C11/4094 ,  G11C17/12

摘要： According to the invention, mounting area is decreased and yield is improved by decreasing the number of elements, and a memory with less burden on peripheral circuitry and a driving method thereof are provided. The invention comprises a memory cell including a memory element in a region where a bit line and a word line cross with an insulator interposed between them, a column decoder, and a selector including a clocked inverter. An input node of the clocked inverter is connected to the bit line while an output node is connected to a data line. Among a plurality of transistors connected in series which form the clocked inverter, a gate of a P-type transistor of which source or drain is connected to a power source on the high potential side VDD and a gate of an N-type transistor of which source or drain is connected to a power source on the low potential side VSS are connected to the column decoder.

摘要翻译： 根据本发明，通过减少元件的数量来减小安装面积并提高产量，并且提供了对外围电路的负担较小的存储器及其驱动方法。 本发明包括一个存储单元，其中存储单元包括位线和字线与插在它们之间的绝缘体交叉的区域中的存储元件，列解码器和包括时钟反相器的选择器。 时钟反相器的输入节点连接到位线，而输出节点连接到数据线。 在形成时钟反相器的串联连接的多个晶体管中，源极或漏极连接到高电位侧VDD上的电源的P型晶体管的栅极和N型晶体管的栅极 源极或漏极连接到低电位侧的电源VSS连接到列解码器。