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公开(公告)号：US11329621B2
公开(公告)日：2022-05-10
申请号：US17064509
申请日：2020-10-06
发明人： Junhyung Lee , Rimal Deep Singh , Johannes Jacobus Emile Maria Hageraats , Joshua Haeseok Cho , Bipul Agarwal , Aravind Kumar Padyana
摘要： Described herein are variable gain amplifiers and multiplexers that embed programmable attenuators into switchable paths to provide variable gain for individual amplifier inputs. The variable gain for an individual input is provided using an amplification stage that is common for each input of the amplifier. A variable attenuation is provided for individual inputs through a combination of a band selection switch and an attenuation selection branch. Individual inputs can be configured to bypass the variable attenuation in a high gain mode.
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52.发明申请公开(公告)号：US20200145039A1
公开(公告)日：2020-05-07
申请号：US16736777
申请日：2020-01-07
发明人： Johannes Jacobus Emile Maria Hageraats , Junhyung Lee , Joshua Haeseok Cho , Aravind Kumar Padyana , Bipul Agarwal
摘要： Described herein are variable-gain amplifier configurations that include a multi-input gain stage, a cascode buffer, and a bypass block. Degeneration switching blocks can be used for the entire multi-input gain stage or for individual input nodes of the multi-input gain stage. This advantageously reduces or eliminates performance penalties in one or more gain modes. The variable impedances can be configured to improve linearity of the amplification process in targeted gain modes. The variable gain amplifier can be configured to provide a low-loss bypass mode in a low gain mode to improve signal quality.
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公开(公告)号：US10348262B2
公开(公告)日：2019-07-09
申请号：US15690762
申请日：2017-08-30
发明人： Junhyung Lee , Rimal Deep Singh , Johannes Jacobus Emile Maria Hageraats , Joshua Haeseok Cho , Bipul Agarwal , Aravind Kumar Padyana
摘要： Described herein are variable gain amplifiers and multiplexers that embed programmable attenuators into switchable paths that allow signals in a high gain mode to bypass attenuation. This advantageously reduces or eliminates performance penalties in the high gain mode. The programmable attenuators can be configured to improve linearity of the amplification process through pre-LNA attenuation in targeted gain modes. In addition, described herein are variable gain amplifiers with embedded attenuators in a switching network. The attenuators can be embedded onto switches and can be configured to have little or no effect on a noise factor in a high gain mode because the switching network can provide an attenuation bypass in a high gain mode and an attenuation in other gain modes. The programmable attenuators can be embedded onto a multi-input LNA architecture.
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公开(公告)号：US09866202B2
公开(公告)日：2018-01-09
申请号：US15408916
申请日：2017-01-18
发明人： Joshua Haeseok Cho , Yunyoung Choi , Bipul Agarwal
CPC分类号： H03H11/245 , H03H11/16 , H04L25/03828
摘要： Digitally controlled attenuators with low phase shift are provided herein. In certain configurations, a digitally controlled attenuator includes an attenuation circuit electrically connected between an input terminal and an output terminal, a bypass circuit electrically connected in parallel with the attenuation circuit between the input terminal and the output terminal, and a plurality of phase compensation capacitors including a first phase compensation capacitor and a second phase compensation capacitor electrically connected in series between the input terminal and the output terminal. The bypass circuit is configured to receive a mode control signal for selecting the bypass circuit to control an amount of attenuation between the input terminal and the output terminal. Additionally, the phase compensation capacitors are operable to compensate for a phase difference between a first signal path through the attenuation circuit and a second signal path through the bypass circuit.
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公开(公告)号：US09806787B2
公开(公告)日：2017-10-31
申请号：US14944951
申请日：2015-11-18
CPC分类号： H04B7/08 , H04B1/0057 , H04B1/40 , H04B7/082 , H04B7/0837 , H04L45/26 , H04W40/04 , H04W40/06 , H04W40/10 , H04W40/246
摘要： Diversity receiver front end system with flexible antenna routing. A receiving system can include a plurality of amplifiers. Each one of the plurality of amplifiers can be disposed along a corresponding one of a plurality of paths between an input of the receiving system and an output of the receiving system. Each one of the plurality of paths can correspond to a different frequency band. The receiving system can include an input multiplexer configured to receive, at one or more of a plurality of input multiplexer inputs, one or more RF signals. Each one of the one or more RF signals can include one or more frequency bands. The input multiplexer can be configured to output each of the one or more RF signals to one or more of a plurality of input multiplexer outputs. The receiving system can include a controller configured to receive an antenna configuration signal and, based on the antenna configuration signal, control the input multiplexer to route each of the one or more RF signals to propagate along one or more of the plurality of paths corresponding to the one of more frequency bands of the RF signal.
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公开(公告)号：US09755577B2
公开(公告)日：2017-09-05
申请号：US14974615
申请日：2015-12-18
CPC分类号： H03F1/0205 , H03F1/3205 , H03F1/3241 , H03F1/3276 , H03F3/193 , H03F3/21 , H03F3/245 , H03F2200/18 , H03F2200/405 , H03F2200/451 , H03F2200/555 , H03F2201/3215 , H03G3/3042 , H04B1/0475 , H04B2001/0425
摘要： A power amplifier circuit includes an amplifier MOSFET and a predistorter MOSFET. The predistorter MOSFET source and drain are connected together, and the predistorter MOSFET is connected between the gate of the amplifier MOSFET and a second bias voltage signal. This biasing of the predistorter MOSFET causes it to provide a nonlinear capacitance at the gate of the amplifier MOSFET. The combined non-linear capacitances of the amplifier MOSFET and predistorter MOSFET provide predistortion that promotes cancellation of the distortion or nonlinearity contributed by the amplifier MOSFET alone.
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公开(公告)号：US20170126208A1
公开(公告)日：2017-05-04
申请号：US15408916
申请日：2017-01-18
发明人： Joshua Haeseok Cho , Yunyoung Choi , Bipul Agarwal
CPC分类号： H03H11/245 , H03H11/16 , H04L25/03828
摘要： Digitally controlled attenuators with low phase shift are provided herein. In certain configurations, a digitally controlled attenuator includes an attenuation circuit electrically connected between an input terminal and an output terminal, a bypass circuit electrically connected in parallel with the attenuation circuit between the input terminal and the output terminal, and a plurality of phase compensation capacitors including a first phase compensation capacitor and a second phase compensation capacitor electrically connected in series between the input terminal and the output terminal. The bypass circuit is configured to receive a mode control signal for selecting the bypass circuit to control an amount of attenuation between the input terminal and the output terminal. Additionally, the phase compensation capacitors are operable to compensate for a phase difference between a first signal path through the attenuation circuit and a second signal path through the bypass circuit.
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58.发明授权公开(公告)号：US09584096B2
公开(公告)日：2017-02-28
申请号：US14704291
申请日：2015-05-05
发明人： Joshua Haeseok Cho , Yunyoung Choi , Bipul Agarwal
CPC分类号： H03H11/245 , H03H11/16 , H04L25/03828
摘要： Apparatus and methods for digital step attenuators are provided herein. In certain configurations, a digital step attenuator (DSA) includes a plurality of DSA stages arranged in a cascade between an input terminal and an output terminal. Each of the DSA stages can be operated in an attenuation mode or in a bypass mode. The DSA further includes an attenuation control circuit, which can be used to control the modes of operation of the DSA stages. The attenuation control circuit can be used to operate the DSA over a plurality of attenuation steps, which can be digitally selectable. To provide low phase shift across the range of attenuation steps, a DSA stage can include one or more phase compensation capacitors used to provide low phase shift and to compensate for a phase difference between the DSA stage operating in the bypass mode and in the attenuation mode.
摘要翻译： 本文提供了用于数字步进衰减器的装置和方法。 在某些配置中，数字步进衰减器（DSA）包括在输入端子和输出端子之间级联布置的多个DSA级。 每个DSA级可以在衰减模式或旁路模式下工作。 DSA还包括一个衰减控制电路，可用于控制DSA级的工作模式。 衰减控制电路可以用于在多个衰减步骤中操作DSA，其可以是数字可选择的。 为了在衰减步骤的范围内提供低相移，DSA级可以包括一个或多个相位补偿电容器，用于提供低相移并补偿在旁路模式和衰减模式下工作的DSA级之间的相位差 。
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公开(公告)号：US20160380656A1
公开(公告)日：2016-12-29
申请号：US15197302
申请日：2016-06-29
CPC分类号： H04B1/0475 , H03F3/24 , H03H11/1291 , H03H2011/0494 , H04B1/3833 , H04B2001/0408 , H04W52/0261 , Y02D70/00 , Y02D70/1222 , Y02D70/40
摘要： A programmable-current transmit continuous-time filter (TX-CTF) system can be included in a radio frequency (RF) transmitter. The input of the TX-CTF can receive a baseband transmission signal, and the output of the TX-CTF can be provided to an upconversion mixer for conversion to RF for transmission. The TX-CTF includes amplifier circuitry and passive circuitry that together define the filter parameters. The TX-CTF further includes programmable current circuitry that provides a programmable bias current to the amplifier circuitry. The TX-CTF system also includes control logic that receives one or more transmitter control signals and, in response, generates signals that control the bias current provided to the TX-CTF.
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60.发明申请公开(公告)号：US20160373123A1
公开(公告)日：2016-12-22
申请号：US15239095
申请日：2016-08-17
CPC分类号： H03L7/1978 , H03L7/1976 , H03M3/422 , H03M3/436 , H03M7/3022 , H04B1/40 , H04B2001/0491 , H04L7/0331 , H04L27/00 , H04L27/361
摘要： A fractional-N divider of a frequency synthesizer is driven by a dither-less and seed-less multi-stage noise shaping (MASH) modulator to alleviate fractional spurious tones introduced by the cyclic train of division ratios from delta-sigma modulators. The MASH modulator includes at least two cascaded dither-less delta-sigma modulators where each modulator includes a first feedback loop the generates the modulator feedback signal, a second feedback loop that disrupts fractional spurious tones and a third feedback loop that provides approximately zero static error. The MASH modulator further includes a combining circuit delays at least one code sequence from at least one of the delta-sigma modulators and that combines the code sequence generated by each of the delta-sigma modulators and at least one delayed code sequence.
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