公开(公告)号：US07650457B2

公开(公告)日：2010-01-19

申请号：US11559323

申请日：2006-11-13

申请人： Hermann Ruckerbauer

发明人： Hermann Ruckerbauer

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/02 ,  G06F12/06 ,  G11C5/02 ,  G11C5/06

CPC分类号： G06F11/1012 ,  G11C5/04

摘要： A memory module stores data in the form of code words, each code word comprising useful bits and check bits for error correction. The memory module contains a first group of the memory devices including check bits and a second group of the memory devices including useful bits, the second group memory devices forming ranks, each rank being addressed as a whole, the ranks forming rank groups, each rank group including at least two ranks and a first group memory device. The memory module further contains a connecting device transferring bit packets each containing useful bits and check bits in the parallel format between an interface of the memory module and the memory devices of a selected rank group.

摘要翻译： 存储器模块以码字的形式存储数据，每个码字包括有用位和用于纠错的校验位。 存储器模块包括第一组存储器件，包括校验位和包括有用位的第二组存储器件，构成等级的第二组存储器件，每个等级作为整体寻址，排列形成等级组，每个等级 组包括至少两个等级和第一组存储设备。 存储器模块还包括一个连接装置，其传送每个包含有用位的位分组，并且以存储器模块的接口和所选择的等级组的存储器件之间的并行格式的校验位进行传送。

公开(公告)号：US20090219063A1

公开(公告)日：2009-09-03

申请号：US12040473

申请日：2008-02-29

申请人： Daniel Kehrer ,  Hermann Ruckerbauer ,  Martin Streibl

发明人： Daniel Kehrer ,  Hermann Ruckerbauer ,  Martin Streibl

IPC分类号： H03B19/00

CPC分类号： G06F1/10 ,  H03K23/40

摘要： Embodiments of the invention relate to an integrated circuit comprising at least one functional unit configured to operate at a first clock frequency. The integrated circuit also comprises at least one first interconnect originating from a contact pad and leading to at least one frequency divider configured to receive a clock signal having a second frequency and generate one or more clock signals to operate the functional unit at the first frequency. The integrated circuit further comprises at least one second interconnect coupling an output of the frequency divider and an input of the functional unit, wherein a total length of the second wired interconnect is less than a total length of the first wired interconnects.

摘要翻译： 本发明的实施例涉及一种集成电路，其包括被配置为以第一时钟频率操作的至少一个功能单元。 集成电路还包括源自接触焊盘的至少一个第一互连件，并且通向至少一个分频器，该至少一个分频器配置成接收具有第二频率的时钟信号，并产生一个或多个时钟信号以在第一频率下操作功能单元。 集成电路还包括耦合分频器的输出和功能单元的输入的至少一个第二互连，其中第二有线互连的总长度小于第一有线互连的总长度。

公开(公告)号：US20090141576A1

公开(公告)日：2009-06-04

申请号：US11949639

申请日：2007-12-03

申请人： Hermann Ruckerbauer

发明人： Hermann Ruckerbauer

IPC分类号： G11C11/406

CPC分类号： G11C11/406 ,  G11C7/04 ,  G11C11/40626 ,  G11C2211/4061

摘要： An integrated device comprising a storage location, wherein data stored in the storage location is repeatedly refreshed with a first predetermined refresh rate during a first period of time. The first period of time provides a first predetermined duration. After the end of the first period of time, the data is repeatedly refreshed with a second predetermined refresh rate.

摘要翻译： 一种包括存储位置的集成设备，其中存储在所述存储位置中的数据在第一时间段期间以第一预定刷新率重复地刷新。 第一时间段提供第一预定持续时间。 在第一时间段结束之后，数据以第二预定刷新率反复刷新。

公开(公告)号：US20090039915A1

公开(公告)日：2009-02-12

申请号：US11834617

申请日：2007-08-06

申请人： Hermann Ruckerbauer ,  Dominique Savignac

发明人： Hermann Ruckerbauer ,  Dominique Savignac

IPC分类号： G06F7/38 ,  H03K19/173

CPC分类号： G11C5/04 ,  G11C5/02 ,  G11C7/10 ,  G11C29/1201 ,  G11C2029/0407 ,  H01L2224/16145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/00

摘要： An integrated circuit includes a first connection and a memory circuit. The integrated circuit is switchable between a master mode of operation, in which a buffer between the first connection and the memory circuit is activated, and a slave mode of operation, in which the buffer between the first connection and the memory circuit is deactivated.

摘要翻译： 集成电路包括第一连接和存储电路。 集成电路可以在其中第一连接和存储器电路之间的缓冲器被激活的主操作模式和从动操作模式之间切换，其中第一连接和存储器电路之间的缓冲器被停用。

公开(公告)号：US07477717B2

公开(公告)日：2009-01-13

申请号：US10831001

申请日：2004-04-23

申请人： Maksim Kuzmenka ,  Hermann Ruckerbauer

发明人： Maksim Kuzmenka ,  Hermann Ruckerbauer

IPC分类号： H03M9/00

CPC分类号： H03M9/00

摘要： An input receiver circuit is provided for receiving a noisy high-speed input signal and for generating a plurality of output signals that can be processed at a low acquisition speed compared to the speed of the high-speed input signal. The input receiver circuit includes an input for receiving the high-speed input signal (data), a plurality of integration elements and a switch for connecting the input to one of the plurality of integration elements for integrating the high-speed input signal. The input receiver circuit further includes a plurality of means for receiving one of the integrated high-speed input signals at a time and for outputting one of the plurality of output signals at a time, and a controller for controlling the switch.

摘要翻译： 提供输入接收器电路，用于接收噪声高速输入信号并产生与高速输入信号的速度相比可以以低采集速度处理的多个输出信号。 输入接收电路包括用于接收高速输入信号（数据）的输入端，多个积分元件和用于将输入连接到多个积分元件中的一个用于积分高速输入信号的开关。 输入接收电路还包括多个用于一次接收集成高速输入信号之一并用于一次输出多个输出信号中的一个的装置，以及用于控制开关的控制器。

公开(公告)号：US07376802B2

公开(公告)日：2008-05-20

申请号：US10850382

申请日：2004-05-21

申请人： Georg Braun ,  Hermann Ruckerbauer ,  Maksim Kuzmenka ,  Siva Raghuram

发明人： Georg Braun ,  Hermann Ruckerbauer ,  Maksim Kuzmenka ,  Siva Raghuram

IPC分类号： G06F12/00 ,  G06F13/00

CPC分类号： G11C7/10 ,  G06F13/1678

摘要： The present invention relates to a memory arrangement having a controller and having at least one memory device. Data signals, control signals and address signals can be transferred between the controller and the memory device. The memory arrangement is designed in such a way that the data signals can be transferred via data signal lines between the controller and the memory device. The memory arrangement is furthermore designed in such a way that the control signals and the address signals can likewise be transferred via the data signal lines between the controller and the memory device.

摘要翻译： 本发明涉及一种具有控制器并具有至少一个存储器件的存储器装置。 数据信号，控制信号和地址信号可以在控制器和存储器件之间传输。 存储器布置被设计成使得数据信号可以通过控制器和存储器件之间的数据信号线传送。 此外，存储器布置被设计成使得控制信号和地址信号同样能够经由控制器和存储器件之间的数据信号线传送。

公开(公告)号：US20070194447A1

公开(公告)日：2007-08-23

申请号：US11657407

申请日：2007-01-24

申请人： Hermann Ruckerbauer

发明人： Hermann Ruckerbauer

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/50 ,  G11C5/02 ,  G11C5/04 ,  G11C5/063 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L25/105 ,  H01L2224/05008 ,  H01L2224/05026 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15331 ,  H01L2224/05599 ,  H01L2224/05099

摘要： A semiconductor component includes an integrated semiconductor chip and a chip housing. The chip housing has first, second, third and fourth conductor tracks that connect input and output connections of the semiconductor chip to external contact connections on the underside and top side of the chip housing in such a way that a loop back interconnection of a plurality of semiconductor components stacked one on top of another is made possible without subsequent structural alterations to the chip housings thereof.

摘要翻译： 半导体部件包括集成半导体芯片和芯片壳体。 芯片壳体具有将半导体芯片的输入和输出连接连接到芯片壳体的下侧和顶侧上的外部接触连接的第一，第二，第三和第四导体轨迹，使得多个 使其一个堆叠在另一个之上的半导体部件成为可能，而不会对其芯片壳体进行后续的结构改变。

公开(公告)号：US20070194446A1

公开(公告)日：2007-08-23

申请号：US11657387

申请日：2007-01-24

申请人： Hermann Ruckerbauer

发明人： Hermann Ruckerbauer

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H05K1/14 ,  G11C5/04 ,  H01L2924/15311 ,  H05K1/0295 ,  H05K1/117 ,  H05K3/222 ,  H05K2201/044 ,  H05K2201/09954 ,  H05K2201/10159 ,  H05K2201/10189 ,  H05K2201/10204

摘要： A memory module is proposed which has a first contact bank at a first edge of its electronic printed circuit board and a second contact bank at a second edge. The printed circuit board has first lines that reach from the first contact bank as far as input connections of at least some of the semiconductor components. The printed circuit board has second conductor lines that reach from output connections of at least some of the semiconductor components as far as the first contact bank. The printed circuit board has third conductor lines that reach from output connections of at least some of the semiconductor components as far as the second contact bank. The printed circuit board has fourth conductor lines that reach from the second contact bank as far as input connections of at least some of the semiconductor components.

摘要翻译： 提出一种存储器模块，其在其电子印刷电路板的第一边缘处具有第一触点组，在第二边缘处具有第二触点组。 印刷电路板具有从第一触点组到达至少一些半导体部件的输入连接的第一线。 印刷电路板具有从至少一些半导体部件的输出连接到达第一触点组的第二导体线。 印刷电路板具有从至少一些半导体部件的输出连接到达第二触点组的第三导体线。 印刷电路板具有从第二触点组到达至少一些半导体部件的输入连接的第四导体线。

公开(公告)号：US20070150792A1

公开(公告)日：2007-06-28

申请号：US11559323

申请日：2006-11-13

申请人： Hermann Ruckerbauer

发明人： Hermann Ruckerbauer

IPC分类号： G11C29/00

CPC分类号： G06F11/1012 ,  G11C5/04

摘要： A memory module stores data in the form of code words, each code word comprising useful bits and check bits for error correction. The memory module contains a first group of the memory devices including check bits and a second group of the memory devices including useful bits, the second group memory devices forming ranks, each rank being addressed as a whole, the ranks forming rank groups, each rank group including at least two ranks and a first group memory device. The memory module further contains a connecting device transferring bit packets each containing useful bits and check bits in the parallel format between an interface of the memory module and the memory devices of a selected rank group

摘要翻译： 存储器模块以码字的形式存储数据，每个码字包括有用位和用于纠错的校验位。 存储器模块包括第一组存储器件，包括校验位和包括有用位的第二组存储器件，构成等级的第二组存储器件，每个等级作为整体寻址，排列形成等级组，每个等级 组包括至少两个等级和第一组存储设备。 存储器模块还包括一个连接装置，其传送每个包含有用位的位分组，并且以存储器模块的接口和所选择的等级组的存储器件之间的并行格式的校验位

公开(公告)号：US07222271B2

公开(公告)日：2007-05-22

申请号：US10133795

申请日：2002-04-26

申请人： Hermann Ruckerbauer ,  Florian Schamberger

发明人： Hermann Ruckerbauer ,  Florian Schamberger

IPC分类号： G11C29/00

CPC分类号： G11C29/78

摘要： Method for repairing hardware faults in memory chips. According to one embodiment, a method is provided for repairing bit errors in memory chips having a multiplicity of memory cells. The method can include detecting bit errors using an error identification algorithm. Further, the method can include determining the addresses of faulty memory cells. The method can also include setting a data bit initiating a repair mode in response to detecting a bit error. In the repair mode, a signal present on a data line to the memory chips can be interpreted as a repair command to perform a repair. In addition, the method can include repairing the bit errors by activating redundant memory cells.

摘要翻译： 修复存储芯片硬件故障的方法。 根据一个实施例，提供了一种用于修复具有多个存储器单元的存储器芯片中的位错误的方法。 该方法可以包括使用错误识别算法检测比特错误。 此外，该方法可以包括确定故障存储器单元的地址。 该方法还可以包括响应于检测到位错误而设置启动修复模式的数据位。 在修复模式中，存在于存储器芯片的数据线上的信号可被解释为执行修复的修复命令。 此外，该方法可以包括通过激活冗余存储器单元来修复位错误。