公开(公告)号：US20080081471A1

公开(公告)日：2008-04-03

申请号：US11736939

申请日：2007-04-18

申请人： Patrick Press ,  Karla Romero ,  Martin Trentzsch ,  Karsten Wieczorek ,  Thomas Feudel ,  Markus Lenski ,  Rolf Stephan

发明人： Patrick Press ,  Karla Romero ,  Martin Trentzsch ,  Karsten Wieczorek ,  Thomas Feudel ,  Markus Lenski ,  Rolf Stephan

IPC分类号： H01L21/44

CPC分类号： H01L21/268 ,  H01L21/823807 ,  H01L27/11 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/7833 ,  H01L29/7843

摘要： By performing sophisticated anneal techniques, such as laser anneal, flash anneal and the like, for a metal silicide formation, such as nickel silicide, the risk of nickel silicide defects in sensitive device regions, such as SRAM pass gates, may be significantly reduced. Also, the activation of dopants may be performed in a highly localized manner, so that undue damage of gate insulation layers may be avoided when activating and re-crystallizing drain and source regions.

摘要翻译： 通过对诸如硅化镍之类的金属硅化物形成进行诸如激光退火，闪光退火等复杂的退火技术，可以显着地减少诸如SRAM通孔之类的敏感器件区域中的硅化镍缺陷的风险。 此外，可以以高度局部化的方式执行掺杂剂的激活，使得当激活和再结晶漏极和源极区域时，可以避免栅极绝缘层的过度损坏。

公开(公告)号：US20080003825A1

公开(公告)日：2008-01-03

申请号：US11672329

申请日：2007-02-07

申请人： Roland Stejskal ,  Stephan Kruegel ,  Markus Lenski

发明人： Roland Stejskal ,  Stephan Kruegel ,  Markus Lenski

IPC分类号： H01L21/302

CPC分类号： H01L21/28123 ,  H01L29/78

摘要： By performing an anisotropic resist modification prior to the actual resist trimming process, the profile of the end portions of the resist features may be significantly enhanced, for instance by providing substantially vertical sidewall portions. Consequently, an overlap of gate electrodes with the respective isolation structures may be obtained, while nevertheless the probability for a short circuit between opposing end portions of the gate electrodes may be significantly reduced, thereby providing the potential for further scaling down device dimensions.

摘要翻译： 通过在实际的抗蚀剂修剪工艺之前进行各向异性抗蚀剂改性，例如通过提供基本上垂直的侧壁部分，可以显着地增强抗蚀剂特征端部的轮廓。 因此，可以获得栅极与各个隔离结构的重叠，然而，可以显着减小栅电极的相对端部之间的短路的可能性，从而提供进一步缩小器件尺寸的可能性。

公开(公告)号：US20080001178A1

公开(公告)日：2008-01-03

申请号：US11674713

申请日：2007-02-14

申请人： Andreas Gehring ,  Ralf Van Bentum ,  Markus Lenski

发明人： Andreas Gehring ,  Ralf Van Bentum ,  Markus Lenski

IPC分类号： H01L29/76 ,  H01L29/745

CPC分类号： H01L27/092 ,  H01L21/823412 ,  H01L21/82345 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7845 ,  H01L29/7848

摘要： By forming a stressed semiconductor material in a gate electrode, a biaxial tensile strain may be induced in the channel region, thereby significantly increasing the charge carrier mobility. This concept may be advantageously combined with additional strain-inducing sources, such as embedded strained semiconductor materials in the drain and source regions, thereby providing the potential for enhancing transistor performance without contributing to process complexity.

摘要翻译： 通过在栅电极中形成应力半导体材料，可以在沟道区域中诱发双轴拉伸应变，从而显着提高载流子迁移率。 该概念可以有利地与额外的应变诱发源（例如在漏极和源极区域中的嵌入式应变半导体材料）结合，从而提供增强晶体管性能的潜力，而不会造成工艺复杂性。

公开(公告)号：US20050142828A1

公开(公告)日：2005-06-30

申请号：US10987827

申请日：2004-11-12

申请人： Thorsten Kammler ,  Katja Huy ,  Markus Lenski

发明人： Thorsten Kammler ,  Katja Huy ,  Markus Lenski

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/786 ,  H01L21/8249 ,  H01L21/3205

CPC分类号： H01L29/66507 ,  H01L21/28052 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66772 ,  H01L29/78621

摘要： The present invention provides a technique that enables the formation of a recessed spacer element by using an anisotropically deposited etch stop layer. Accordingly, in subsequent cleaning processes, material residues of the etch stop layer may be efficiently removed from upper sidewall portions of a line element, thereby increasing the available area for a diffusion path in a subsequent silicidation process. The anisotropic deposition of the etch stop layer may be accomplished by high density plasma enhanced CVD or by directional sputter techniques.

摘要翻译： 本发明提供一种能够通过使用各向异性沉积的蚀刻停止层形成凹陷间隔元件的技术。 因此，在随后的清洗过程中，可以有效地从线元件的上侧壁部分去除蚀刻停止层的材料残留物，从而增加随后的硅化工艺中扩散路径的可用面积。 蚀刻停止层的各向异性沉积可以通过高密度等离子体增强CVD或定向溅射技术来实现。

公开(公告)号：US08765586B2

公开(公告)日：2014-07-01

申请号：US13331842

申请日：2011-12-20

申请人： Clemens Fitz ,  Peter Baars ,  Markus Lenski

发明人： Clemens Fitz ,  Peter Baars ,  Markus Lenski

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/76897 ,  H01L21/28518 ,  H01L21/28556 ,  H01L21/76814 ,  H01L29/41783 ,  H01L29/66545

摘要： Disclosed herein are various methods of forming metal silicide regions on semiconductor devices. In one example, the method includes forming a sacrificial gate structure above a semiconducting substrate, performing a selective metal silicide formation process to form metal silicide regions in source/drain regions formed in or above the substrate, after forming the metal silicide regions, removing the sacrificial gate structure to define a gate opening and forming a replacement gate structure in the gate opening, the replacement gate structure comprised of at least one metal layer.

摘要翻译： 本文公开了在半导体器件上形成金属硅化物区域的各种方法。 在一个示例中，该方法包括在半导体衬底之上形成牺牲栅极结构，在形成金属硅化物区域之后，执行选择性金属硅化物形成工艺以形成在衬底中或上方形成的源极/漏极区域中的金属硅化物区域， 牺牲栅极结构以限定栅极开口并在栅极开口中形成替代栅极结构，所述替换栅极结构由至少一个金属层组成。

公开(公告)号：US08530894B2

公开(公告)日：2013-09-10

申请号：US13474934

申请日：2012-05-18

申请人： Anthony Mowry ,  Casey Scott ,  Vassilios Papageorgiou ,  Andy Wei ,  Markus Lenski ,  Andreas Gehring

发明人： Anthony Mowry ,  Casey Scott ,  Vassilios Papageorgiou ,  Andy Wei ,  Markus Lenski ,  Andreas Gehring

IPC分类号： H01L21/00

CPC分类号： H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L22/34 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833

摘要： By providing a test structure for evaluating the patterning process and/or the epitaxial growth process for forming embedded semiconductor alloys in sophisticated semiconductor devices, enhanced statistical relevance in combination with reduced test time may be accomplished.

摘要翻译： 通过提供用于评估用于在复杂半导体器件中形成嵌入式半导体合金的图案化工艺和/或外延生长工艺的测试结构，可以实现与减少的测试时间相结合的增强的统计相关性。

公开(公告)号：US08329526B2

公开(公告)日：2012-12-11

申请号：US12905655

申请日：2010-10-15

申请人： Jens Heinrich ,  Frank Seliger ,  Ralf Richter ,  Markus Lenski

发明人： Jens Heinrich ,  Frank Seliger ,  Ralf Richter ,  Markus Lenski

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/8238

CPC分类号： H01L21/823828 ,  H01L21/823807 ,  H01L29/7843

摘要： Dielectric cap layers of sophisticated high-k metal gate electrode structures may be efficiently removed on the basis of a sacrificial fill material, thereby reliably preserving integrity of a protective sidewall spacer structure, which in turn may result in superior uniformity of the threshold voltage of the transistors. The sacrificial fill material may be provided in the form of an organic material that may be reduced in thickness on the basis of a wet developing process, thereby enabling a high degree of process controllability.

摘要翻译： 可以基于牺牲填充材料有效地去除复杂的高k金属栅极电极结构的介电盖层，从而可靠地保持保护性侧壁间隔结构的完整性，这又可以导致优异的阈值电压均匀性 晶体管。 牺牲填充材料可以以有机材料的形式提供，其可以基于湿式显影工艺而减小厚度，从而能够实现高度的工艺可控性。

公开(公告)号：US08324108B2

公开(公告)日：2012-12-04

申请号：US13034777

申请日：2011-02-25

申请人： Ralf Richter ,  Markus Lenski ,  Torsten Huisinga

发明人： Ralf Richter ,  Markus Lenski ,  Torsten Huisinga

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/823807 ,  H01L21/31111 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/53295 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a dual stress liner approach, unwanted material provided between closely spaced gate electrode structures may be removed to a significant degree on the basis of a wet chemical etch process, thereby reducing the risk of creating patterning-related irregularities. Consequently, the probability of contact failures in sophisticated interlayer dielectric material systems formed on the basis of a dual stress liner approach may be reduced.

摘要翻译： 在双应力衬垫方法中，在紧密间隔开的栅电极结构之间提供的不需要的材料可以在湿化学蚀刻工艺的基础上被去除，从而降低产生图案相关不规则性的风险。 因此，可以减少基于双应力衬垫方法形成的复杂层间绝缘材料系统中的接触故障的可能性。

公开(公告)号：US20110230039A1

公开(公告)日：2011-09-22

申请号：US13152350

申请日：2011-06-03

申请人： Anthony Mowry ,  Markus Lenski ,  Guido Koerner ,  Ralf Otterbach

发明人： Anthony Mowry ,  Markus Lenski ,  Guido Koerner ,  Ralf Otterbach

IPC分类号： H01L21/265

CPC分类号： H01L21/823864 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659

摘要： By selectively modifying the spacer width, for instance, by reducing the spacer width on the basis of implantation masks, an individual adaptation of dopant profiles may be achieved without unduly contributing to the overall process complexity. For example, in sophisticated integrated circuits, the performance of transistors of the same or different conductivity type may be individually adjusted by providing different sidewall spacer widths on the basis of an appropriate masking regime.

摘要翻译： 通过例如通过基于注入掩模减小间隔物宽度来选择性地修改间隔物宽度，可以实现单独的掺杂剂轮廓的适应性，而不会不利地导致整个工艺复杂性。 例如，在复杂的集成电路中，相同或不同导电类型的晶体管的性能可以通过基于适当的掩蔽状态提供不同的侧壁间隔物宽度来单独调节。

公开(公告)号：US20110104863A1

公开(公告)日：2011-05-05

申请号：US12894579

申请日：2010-09-30

申请人： Sven Beyer ,  Thilo Scheiper ,  Jan Hoentschel ,  Markus Lenski

发明人： Sven Beyer ,  Thilo Scheiper ,  Jan Hoentschel ,  Markus Lenski

IPC分类号： H01L21/336

CPC分类号： H01L21/28238 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/51 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7848

摘要： When forming sophisticated high-k metal gate electrode structures in an early manufacturing stage, the dielectric cap layer of the gate electrode structures may be efficiently removed on the basis of a carbon spacer element, which may thus preserve the integrity of the silicon nitride spacer structure. Thereafter, the sacrificial carbon spacer may be removed substantially without affecting other device areas, such as isolation structures, active regions and the like, which may contribute to superior process conditions during the further processing of the semiconductor device.

摘要翻译： 当在早期制造阶段形成复杂的高k金属栅电极结构时，可以基于碳间隔元件有效地去除栅电极结构的电介质盖层，这可以保持氮化硅间隔结构的完整性 。 此后，可以基本上除去牺牲碳隔离物而不影响其它器件区域，例如隔离结构，有源区等，这可能有助于在半导体器件的进一步处理期间优良的工艺条件。