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公开(公告)号：US08179159B1
公开(公告)日：2012-05-15
申请号：US13116276
申请日：2011-05-26
IPC分类号： H03K19/173 , G06F7/38
CPC分类号： H03K19/17736
摘要： A method of configuring a stacked integrated circuit (“IC”) having a first IC die with configurable logic and a second IC die electrically coupled to the first IC die through an array of inter-chip contacts includes: providing a frame having frame data and a frame address in a frame header to the first IC die; storing the frame data in a frame data register of the first IC die; processing the frame header to determine whether a frame destination is in the first IC die or the second IC die; in response to determining that the frame destination is in the second IC die, providing the frame address to the second IC die through an inter-chip frame address bus including a first plurality of the array of inter-chip contacts; and writing the frame data from the frame data register of the first IC die to the frame destination through an inter-chip frame data bus including a second plurality of the array of inter-chip contacts.
摘要翻译： 一种配置具有可配置逻辑的第一IC芯片的堆叠集成电路（“IC”）和通过芯片间触点阵列电耦合到第一IC裸片的第二IC裸片的方法包括：提供具有帧数据的帧和 第一IC芯片的帧头中的帧地址; 将帧数据存储在第一IC芯片的帧数据寄存器中; 处理帧头以确定帧目的地是否在第一IC管芯或第二IC管芯中; 响应于确定帧目的地在第二IC芯片中，通过包括第一多个芯片间接触阵列的片间帧地址总线将第二IC芯片提供帧地址; 以及通过包括第二多个芯片间接触阵列的片间帧数据总线将帧数据从第一IC芯片的帧数据寄存器写入帧目的地。
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公开(公告)号：US08166366B1
公开(公告)日：2012-04-24
申请号：US11975961
申请日：2007-10-22
CPC分类号： G06F11/10
摘要： Partial configuration of programmable circuitry with validation for an integrated circuit is described. An integrated circuit with programmable circuitry is obtained. The programmable circuitry is configured with a first bitstream in a non-dynamic mode of operation, after which the integrated circuit includes a configuration controller coupled to a buffer, an internal configuration access port, and an error checker. A portion of a second bitstream is loaded into the buffer for a dynamic partial configuration mode of operation. The portion of the second bitstream loaded into the buffer is validated with the error checker as being acceptable, after which the portion of the second bitstream is instantiated in the programmable circuitry via the internal configuration access port.
摘要翻译： 描述了具有集成电路验证的可编程电路的部分配置。 获得具有可编程电路的集成电路。 可编程电路配置有非动态操作模式的第一比特流，此后，集成电路包括耦合到缓冲器，内部配置访问端口和错误检查器的配置控制器。 第二比特流的一部分被加载到缓冲器中用于动态部分配置操作模式。 加载到缓冲器中的第二比特流的部分用错误检查器验证为可接受的，之后第二比特流的部分经由内部配置访问端口在可编程电路中被实例化。
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公开(公告)号：US07973555B1
公开(公告)日：2011-07-05
申请号：US12128459
申请日：2008-05-28
IPC分类号： H03K19/173 , G06F7/38
CPC分类号： H03K19/17736
摘要： A semiconductor device includes a field-programmable gate array (“FPGA”) die (202) having a frame address bus (604), a frame data bus (608), and a second integrated circuit (“IC”) die (204) attached to the FPGA die. An inter-chip frame address bus (605) couples at least low order frame address bits of a frame address of a frame between the FPGA die and the second IC die. The inter-chip frame address bus includes a first plurality of contacts (614) formed between the FPGA die and the second IC die. An inter-chip frame data bus couples frame data of the frame between the FPGA die and the second IC die. The inter-chip frame data bus includes a second plurality of contacts (616) formed between the FPGA die and the second IC die.
摘要翻译： 半导体器件包括具有帧地址总线（604）的现场可编程门阵列（“FPGA”）管芯（202），帧数据总线（608）和第二集成电路（“IC”）芯片（204） 连接到FPGA模具。 芯片间帧地址总线（605）将至少在FPGA管芯和第二IC管芯之间的帧的帧地址的低位帧地址位耦合。 片间帧地址总线包括形成在FPGA管芯和第二IC管芯之间的第一多个触点（614）。 芯片间帧数据总线将帧的帧数据耦合在FPGA管芯和第二IC管芯之间。 芯片间帧数据总线包括形成在FPGA管芯和第二IC管芯之间的第二多个触点（616）。
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54.发明授权Utilizing multiple test bitstreams to avoid localized defects in partially defective programmable integrated circuits 有权利用多个测试比特流来避免局部缺陷的可编程集成电路中的局部缺陷公开(公告)号：US07849435B1
公开(公告)日：2010-12-07
申请号：US12181344
申请日：2008-07-29
IPC分类号： G06F17/50
CPC分类号： G01R31/318516
摘要： Methods and structures utilizing multiple configuration bitstreams to program integrated circuits (ICs) such as programmable logic devices, thereby enabling the utilization of partially defective ICs. A user design is implemented two or more times, preferably utilizing different programmable resources as much as possible in each configuration bitstream. The resulting user configuration bitstreams are stored along with associated test bitstreams in a memory device, e.g., a programmable read-only memory (PROM). Under the control of a configuration control circuit or device, the test bitstreams are loaded into a partially defective IC and tested using an automated testing procedure. When a test bitstream is found that enables the associated user design to function correctly in the programmed IC, i.e., that avoids the defective programmable resources in the IC, the associated user bitstream is loaded into the IC, the configuration procedure terminates, and the programmed IC begins to function according to the user design.
摘要翻译： 利用多个配置比特流来编程诸如可编程逻辑器件的集成电路（IC）的方法和结构，从而能够利用部分有缺陷的IC。 用户设计实现两次或更多次，优选地在每个配置比特流中尽可能多地使用不同的可编程资源。 生成的用户配置比特流与关联的测试比特流一起存储在存储器设备中，例如可编程只读存储器（PROM）中。 在配置控制电路或设备的控制下，将测试比特流加载到部分有缺陷的IC中，并使用自动测试程序进行测试。 当发现测试比特流使得相关联的用户设计能够在编程的IC中正常工作时，即，避免IC中的有缺陷的可编程资源，相关联的用户比特流被加载到IC中，配置过程终止，并且被编程 IC根据用户设计开始运作。
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公开(公告)号：US07795901B1
公开(公告)日：2010-09-14
申请号：US12468638
申请日：2009-05-19
CPC分类号： H03K19/17756 , G01R31/318516 , H03K19/17764
摘要： A defect is automatically isolated in an integrated circuit device having programmable logic and interconnect circuits. A sequence of configurations is created to route data in a pattern through the programmable logic and interconnect circuits. Each configuration within the sequence is determined (e.g., generated or selected from a plurality of pre-generated configurations) as a function of output data from a prior configuration in the sequence. For each configuration in the sequence, the programmable logic and interconnect circuits are configured with the configuration and an automatic test instrument routes data in the pattern through the programmable logic and interconnect circuits. For each configuration in the sequence, the output data from the programmable logic and interconnect circuits is assessed. For each configuration in the sequence, the assessed output data isolates the defect to a portion of the pattern for the configuration that is within the portion for a prior configuration in the sequence.
摘要翻译： 在具有可编程逻辑和互连电路的集成电路器件中，自动隔离缺陷。 创建一系列配置以通过可编程逻辑和互连电路以图案路由数据。 根据序列中的先前配置的输出数据确定序列内的每个配置（例如，从多个预先生成的配置中生成或选择）。 对于序列中的每个配置，可编程逻辑和互连电路配置为配置，自动测试仪器通过可编程逻辑和互连电路对图案中的数据进行路由。 对于序列中的每个配置，评估来自可编程逻辑和互连电路的输出数据。 对于序列中的每个配置，评估的输出数据将缺陷隔离到用于在序列中先前配置的部分内的配置的模式的一部分。
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公开(公告)号：US07781879B1
公开(公告)日：2010-08-24
申请号：US12503429
申请日：2009-07-15
IPC分类号： H01L23/02
CPC分类号： H01L25/0657 , H01L23/642 , H01L2224/05001 , H01L2224/05008 , H01L2224/05009 , H01L2224/05024 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05164 , H01L2224/05166 , H01L2224/05169 , H01L2224/05171 , H01L2224/05181 , H01L2224/05184 , H01L2224/05568 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05655 , H01L2224/05664 , H01L2224/05666 , H01L2224/05669 , H01L2224/05671 , H01L2224/13025 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/17181 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2924/15311 , H01L2924/19015 , H01L2924/19103 , H01L2924/00014
摘要： Apparatus for integrating capacitors in stacked integrated circuits are described. One aspect of the invention relates to a semiconductor assembly having a carrier substrate, a plurality of integrated circuit dice, and at least one metal-insulator-metal (MIM) capacitor. The integrated circuit dice are vertically stacked on the carrier substrate. Each MIM capacitor is disposed between a first integrated circuit die and a second integrated circuit die of the plurality of integrated circuit dice. The at least one MIM capacitor is fabricated on at least one of a face of the first integrated circuit die and a backside of the second integrated circuit die.
摘要翻译： 描述了用于在堆叠集成电路中集成电容器的装置。 本发明的一个方面涉及一种具有载体衬底，多个集成电路芯片和至少一种金属 - 绝缘体 - 金属（MIM）电容器的半导体组件。 集成电路芯片垂直堆叠在载体基板上。 每个MIM电容器设置在多个集成电路芯片的第一集成电路管芯和第二集成电路管芯之间。 所述至少一个MIM电容器被制造在所述第一集成电路管芯的表面和所述第二集成电路管芯的背面中的至少一个上。
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公开(公告)号：US07716497B1
公开(公告)日：2010-05-11
申请号：US11151985
申请日：2005-06-14
摘要： An external storage device may transmit encrypted configuration data to a PLD during a configuration operation without transmitting the encryption key to the PLD and without retaining decryption information in the PLD. During a set-up operation, the encryption key is provided to the PLD, which generates an ID code upon power-up. The PLD generates a correction word in response to the encryption key and the ID code. The correction word is output from the PLD, which is powered-down, and is stored with the encrypted configuration data in the storage device. Then, during a configuration operation, the PLD is powered-on and re-generates the ID code. The correction word and the encrypted configuration data are transmitted to the PLD, which generates a decryption key in response to the re-generated ID code and the correction word.
摘要翻译： 外部存储装置可以在配置操作期间将加密的配置数据发送到PLD，而不将加密密钥发送到PLD，而不在PLD中保留解密信息。 在设置操作期间，加密密钥被提供给PLD，其在加电时产生ID代码。 PLD响应于加密密钥和ID码产生校正字。 校正字从PLD输出，其被断电，并且与加密的配置数据一起存储在存储设备中。 然后，在配置操作期间，PLD被通电并重新生成ID码。 校正字和加密的配置数据被发送到PLD，PLD响应于重新产生的ID码和校正字产生解密密钥。
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公开(公告)号：US07619438B1
公开(公告)日：2009-11-17
申请号：US11974354
申请日：2007-10-11
IPC分类号： H03K19/003
CPC分类号： H03K19/17764 , G01R31/318516
摘要： Methods of enabling the use of defective programmable devices. The method comprises performing functional testing for each programmable device of a plurality of programmable devices; identifying each programmable device of the plurality of programmable devices having a defective portion of programmable blocks; identifying, for each programmable device which is identified to have a defective portion of programmable blocks, a location of the defective portion; and storing, for each programmable device which is identified to have a defective portion of programmable blocks, the location of the defective portion on the programmable device.
摘要翻译： 使用有缺陷的可编程器件的方法。 该方法包括对多个可编程设备的每个可编程设备执行功能测试; 识别具有可编程块的缺陷部分的多个可编程设备中的每个可编程设备; 识别被识别为具有可编程块的缺陷部分的每个可编程设备的缺陷部分的位置; 并且对于被识别为具有可编程块的缺陷部分的每个可编程设备，存储可编程设备上的缺陷部分的位置。
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59.发明授权Programmable logic device that supports secure and non-secure modes of decryption-key access 有权可编程逻辑器件，支持安全和非安全的解密密钥访问模式公开(公告)号：US07366306B1
公开(公告)日：2008-04-29
申请号：US10150308
申请日：2002-05-17
CPC分类号： G06F12/1425 , G06F21/57 , G06F21/79 , G06Q20/3829 , H04L9/0637 , H04L9/0897 , H04L2209/34
摘要： Described are programmable logic devices that decrypt proprietary configuration data using on-chip decryption keys. The keys are stored in a key memory that can be operated in a secure mode or a non-secure mode. The non-secure mode allows the decryption keys to be read or written freely; the secure mode bars read and write access to the decryption keys. The programmable logic device supports secure and non-secure modes on a key-by-key basis, allowing users to write, verify, and erase individual keys without affecting others.
摘要翻译： 描述了使用片上解密密钥来解密专有配置数据的可编程逻辑器件。 密钥存储在可以以安全模式或非安全模式操作的密钥存储器中。 非安全模式允许解密密钥被自由读取或写入; 安全模式可以读取和写入对解密密钥的访问。 可编程逻辑器件在逐个密钥的基础上支持安全和非安全模式，允许用户写入，验证和擦除各个密钥，而不影响其他密钥。
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60.发明授权Method and circuit for reducing programmable logic pin counts for large scale logic 有权用于大规模逻辑降低可编程逻辑引脚数的方法和电路公开(公告)号：US07365568B1
公开(公告)日：2008-04-29
申请号：US11699114
申请日：2007-01-29
IPC分类号： H03K19/177 , H01L25/00
CPC分类号： H03K19/1732 , H05K1/029 , H05K2201/09127 , H05K2201/10212 , H05K2201/10689
摘要： A circuit board includes a large scale logic device and at least one outrigger device wherein signals having a transmission delay budget that exceed a threshold value are produced to the outrigger device for coupling to circuit devices of the circuit board that are external to the large scale logic device. One embodiment of the invention comprises a plurality of outrigger devices that communicate with the large scale logic device by way of parallel data buses, as well as multi-gigabit transceiver data lines. Logic within the outrigger devices is generally limited to signal routing and transmission logic. The large scale logic device further comprises logic to transmit and receive signals to and from the outrigger devices in a way that is transparent to internal logic of the large scale logic device.
摘要翻译： 电路板包括大规模逻辑器件和至少一个外伸支架装置，其中具有超过阈值的传输延迟预算的信号被产生到外伸支架装置，用于耦合到大规模逻辑外部的电路板的电路装置 设备。 本发明的一个实施例包括通过并行数据总线以及多吉比特收发器数据线与大规模逻辑设备通信的多个外伸支架设备。 外伸装置内的逻辑通常限于信号路由和传输逻辑。 大规模逻辑设备还包括以对大规模逻辑设备的内部逻辑透明的方式向外伸支架设备发送信号和从外伸支架设备接收信号的逻辑。
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