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    Configuration interface to stacked FPGA
    1.
    发明授权
    Configuration interface to stacked FPGA 有权
    配置接口堆叠FPGA

    公开(公告)号：US08179159B1

    公开(公告)日：2012-05-15

    申请号：US13116276

    申请日：2011-05-26

    申请人： Stephen M. Trimberger ,  Arifur Rahman

    发明人： Stephen M. Trimberger ,  Arifur Rahman

    IPC分类号： H03K19/173 ,  G06F7/38

    CPC分类号： H03K19/17736

    摘要： A method of configuring a stacked integrated circuit (“IC”) having a first IC die with configurable logic and a second IC die electrically coupled to the first IC die through an array of inter-chip contacts includes: providing a frame having frame data and a frame address in a frame header to the first IC die; storing the frame data in a frame data register of the first IC die; processing the frame header to determine whether a frame destination is in the first IC die or the second IC die; in response to determining that the frame destination is in the second IC die, providing the frame address to the second IC die through an inter-chip frame address bus including a first plurality of the array of inter-chip contacts; and writing the frame data from the frame data register of the first IC die to the frame destination through an inter-chip frame data bus including a second plurality of the array of inter-chip contacts.

    摘要翻译： 一种配置具有可配置逻辑的第一IC芯片的堆叠集成电路（“IC”）和通过芯片间触点阵列电耦合到第一IC裸片的第二IC裸片的方法包括：提供具有帧数据的帧和 第一IC芯片的帧头中的帧地址; 将帧数据存储在第一IC芯片的帧数据寄存器中; 处理帧头以确定帧目的地是否在第一IC管芯或第二IC管芯中; 响应于确定帧目的地在第二IC芯片中，通过包括第一多个芯片间接触阵列的片间帧地址总线将第二IC芯片提供帧地址; 以及通过包括第二多个芯片间接触阵列的片间帧数据总线将帧数据从第一IC芯片的帧数据寄存器写入帧目的地。

    Configuration interface to stacked FPGA
    2.
    发明授权
    Configuration interface to stacked FPGA 有权
    配置接口堆叠FPGA

    公开(公告)号：US07973555B1

    公开(公告)日：2011-07-05

    申请号：US12128459

    申请日：2008-05-28

    申请人： Stephen M. Trimberger ,  Arifur Rahman

    发明人： Stephen M. Trimberger ,  Arifur Rahman

    IPC分类号： H03K19/173 ,  G06F7/38

    CPC分类号： H03K19/17736

    摘要： A semiconductor device includes a field-programmable gate array (“FPGA”) die (202) having a frame address bus (604), a frame data bus (608), and a second integrated circuit (“IC”) die (204) attached to the FPGA die. An inter-chip frame address bus (605) couples at least low order frame address bits of a frame address of a frame between the FPGA die and the second IC die. The inter-chip frame address bus includes a first plurality of contacts (614) formed between the FPGA die and the second IC die. An inter-chip frame data bus couples frame data of the frame between the FPGA die and the second IC die. The inter-chip frame data bus includes a second plurality of contacts (616) formed between the FPGA die and the second IC die.

    摘要翻译： 半导体器件包括具有帧地址总线（604）的现场可编程门阵列（“FPGA”）管芯（202），帧数据总线（608）和第二集成电路（“IC”）芯片（204） 连接到FPGA模具。 芯片间帧地址总线（605）将至少在FPGA管芯和第二IC管芯之间的帧的帧地址的低位帧地址位耦合。 片间帧地址总线包括形成在FPGA管芯和第二IC管芯之间的第一多个触点（614）。 芯片间帧数据总线将帧的帧数据耦合在FPGA管芯和第二IC管芯之间。 芯片间帧数据总线包括形成在FPGA管芯和第二IC管芯之间的第二多个触点（616）。

    Software model for a hybrid stacked field programmable gate array
    5.
    发明授权
    Software model for a hybrid stacked field programmable gate array 有权
    混合堆叠现场可编程门阵列的软件模型

    公开(公告)号：US07930661B1

    公开(公告)日：2011-04-19

    申请号：US12185511

    申请日：2008-08-04

    申请人： Stephen M. Trimberger ,  Arifur Rahman ,  Bernard J. New

    发明人： Stephen M. Trimberger ,  Arifur Rahman ,  Bernard J. New

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5054

    摘要： A software model (620) of a stacked integrated circuit system (600) includes a first integrated circuit die (602) connected to a second integrated circuit die (604) through an interchip communication interface (606). A software model of the first integrated circuit die includes an integrated circuit resource (614) and an internal interface (150). A software model of the second integrated circuit die includes a stacked resource (618). The software model of the internal interface is configurable to connect the stacked resource of the second integrated circuit die to the integrated circuit resource through the interchip communication interface.

    摘要翻译： 层叠集成电路系统（600）的软件模型（620）包括通过芯片间通信接口（606）连接到第二集成电路管芯（604）的第一集成电路管芯（602）。 第一集成电路管芯的软件模型包括集成电路资源（614）和内部接口（150）。 第二集成电路管芯的软件模型包括堆叠资源（618）。 内部接口的软件模型可配置为通过芯片间通信接口将第二个集成电路管芯的堆叠资源连接到集成电路资源。

    Semiconductor devices having redundant through-die vias and methods of fabricating the same
    6.
    发明授权
    Semiconductor devices having redundant through-die vias and methods of fabricating the same 有权
    具有冗余通孔的半导体器件及其制造方法

    公开(公告)号：US08058707B1

    公开(公告)日：2011-11-15

    申请号：US12041610

    申请日：2008-03-03

    申请人： Stephen M. Trimberger ,  Arifur Rahman

    发明人： Stephen M. Trimberger ,  Arifur Rahman

    IPC分类号： H01L21/44 ,  H01L23/48 ,  H01L29/41

    CPC分类号： H01L23/528 ,  H01L23/481 ,  H01L25/0652 ,  H01L2224/16225 ,  H01L2924/15311

    摘要： Semiconductor devices having redundant through-die vias (TDVs) and methods of fabricating the same are described. A substrate is provided having conductive interconnect formed on an active side thereof. Through die vias (TDVs) are formed in the substrate between a backside and the active side thereof. The TDVs include signal TDVs, redundant TDVs (i.e., redundant signal TDVs), and power supply TDVs. The signal TDVs are spaced apart from the redundant TDVs to form a pattern of TDV pairs. The power supply TDVs are interspersed among the TDV pairs. The conductive interconnect includes first signal conductors electrically coupling each of the signal TDVs to a respective one of the redundant TDVs defining a respective one of the TDV pairs.

    摘要翻译： 描述了具有冗余通孔（TDV）的半导体器件及其制造方法。 提供了在其活性侧形成有导电互连的衬底。 通过裸片（TDV）形成在基板的背侧和其活动侧之间。 TDV包括信号TDV，冗余TDV（即，冗余信号TDV）和电源TDV。 信号TDV与冗余TDV间隔开以形成TDV对的模式。 电源TDV分散在TDV对之间。 导电互连包括将每个信号TDV电耦合到限定TDV对中的相应一个的冗余TDV中的相应一个的第一信号导体。

    Integrated circuit with through-die via interface for die stacking
    7.
    发明授权
    Integrated circuit with through-die via interface for die stacking 有权
    集成电路，具有通孔接口，用于芯片堆叠

    公开(公告)号：US07518398B1

    公开(公告)日：2009-04-14

    申请号：US11973062

    申请日：2007-10-04

    申请人： Arifur Rahman ,  Stephen M. Trimberger ,  Bernard J. New

    发明人： Arifur Rahman ,  Stephen M. Trimberger ,  Bernard J. New

    IPC分类号： H03K19/173

    CPC分类号： H03K19/17796

    摘要： An integrated circuit with a through-die via (TDV) interface for die stacking is described. One aspect of the invention relates to an integrated circuit die having an array of tiles arranged in columns. The integrated circuit die includes at least one interface tile. Each interface tile includes a logic element, contacts, and through die vias (TDVs). The logic element is coupled to a routing fabric of the integrated circuit die. The contacts are configured to be coupled to conductive interconnect of another integrated circuit die attached to the backside of the integrated circuit die. The TDVs are configured to couple the logic element to the contacts.

    摘要翻译： 描述了具有用于管芯堆叠的通孔（TDV）接口的集成电路。 本发明的一个方面涉及具有排列成列的瓷砖阵列的集成电路管芯。 集成电路管芯包括至少一个界面砖。 每个接口瓦片包括逻辑元件，触点和通孔（TDV）。 逻辑元件耦合到集成电路管芯的布线结构。 触点被配置为耦合到附接到集成电路管芯的背面的另一个集成电路管芯的导电互连。 TDV被配置为将逻辑元件耦合到触点。