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241 条记录 (耗时 0.021 秒)

    Fabrication of germanium nanowire transistors
    52.
    发明授权
    Fabrication of germanium nanowire transistors 有权
    锗纳米线晶体管的制造

    公开(公告)号：US08110458B2

    公开(公告)日：2012-02-07

    申请号：US12762585

    申请日：2010-04-19

    申请人： Been-Yih Jin ,  Jack T. Kavalieros ,  Matthew V. Metz ,  Marko Radosavlievic ,  Robert S. Chau

    发明人： Been-Yih Jin ,  Jack T. Kavalieros ,  Matthew V. Metz ,  Marko Radosavlievic ,  Robert S. Chau

    IPC分类号： H01L21/336

    CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/42392 ,  H01L29/66477 ,  H01L29/78684 ,  H01L29/78696

    摘要： In general, in one aspect, a method includes using the Germanium nanowire as building block for high performance logic, memory and low dimensional quantum effect devices. The Germanium nanowire channel and the SiGe anchoring regions are formed simultaneously through preferential Si oxidation of epitaxial Silicon Germanium epi layer. The placement of the germanium nanowires is accomplished using a Si fin as a template and the germanium nanowire is held on Si substrate through SiGe anchors created by masking the two ends of the fins. High dielectric constant gate oxide and work function metals wrap around the Germanium nanowire for gate-all-around electrostatic channel on/off control, while the Germanium nanowire provides high carrier mobility in the transistor channel region. The germanium nanowire transistors enable high performance, low voltage (low power consumption) operation of logic and memory devices.

    摘要翻译： 通常，在一个方面，一种方法包括使用锗纳米线作为高性能逻辑，存储器和低维量子效应器件的构建块。 锗纳米线通道和SiGe锚定区域通过外延硅锗外延层的优先Si氧化同时形成。 使用Si翅片作为模板来实现锗纳米线的放置，并且锗纳米线通过掩蔽翅片的两端而形成的SiGe锚定件保持在Si衬底上。 高介电常数栅极氧化物和功函数金属缠绕在锗纳米线上，用于门极全静电通道开/关控制，而锗纳米线在晶体管沟道区域提供高载流子迁移率。 锗纳米线晶体管可实现逻辑和存储器件的高性能，低电压（低功耗）操作。

    Fabrication of germanium nanowire transistors
    54.
    发明申请
    Fabrication of germanium nanowire transistors 有权
    锗纳米线晶体管的制造

    公开(公告)号：US20090170251A1

    公开(公告)日：2009-07-02

    申请号：US12006273

    申请日：2007-12-31

    申请人： Been-Yih Jin ,  Jack T. Kavalieros ,  Matthew V. Metz ,  Marko Radosavlievic ,  Robert S. Chau

    发明人： Been-Yih Jin ,  Jack T. Kavalieros ,  Matthew V. Metz ,  Marko Radosavlievic ,  Robert S. Chau

    IPC分类号： H01L21/8234

    CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/42392 ,  H01L29/66477 ,  H01L29/78684 ,  H01L29/78696

    摘要： In general, in one aspect, a method includes using the Germanium nanowire as building block for high performance logic, memory and low dimensional quantum effect devices. The Germanium nanowire channel and the SiGe anchoring regions are formed simultaneously through preferential Si oxidation of epitaxial Silicon Germanium epi layer. The placement of the germanium nanowires is accomplished using a Si fin as a template and the germanium nanowire is held on Si substrate through SiGe anchors created by masking the two ends of the fins. High dielectric constant gate oxide and work function metals wrap around the Germanium nanowire for gate-all-around electrostatic channel on/off control, while the Germanium nanowire provides high carrier mobility in the transistor channel region. The germanium nanowire transistors enable high performance, low voltage (low power consumption) operation of logic and memory devices.

    摘要翻译： 通常，在一个方面，一种方法包括使用锗纳米线作为高性能逻辑，存储器和低维量子效应器件的构建块。 锗纳米线通道和SiGe锚定区域通过外延硅锗外延层的优先Si氧化同时形成。 使用Si翅片作为模板来实现锗纳米线的放置，并且锗纳米线通过掩蔽翅片的两端而形成的SiGe锚定件保持在Si衬底上。 高介电常数栅极氧化物和功函数金属缠绕在锗纳米线上，用于门极全静电通道开/关控制，而锗纳米线在晶体管沟道区域提供高载流子迁移率。 锗纳米线晶体管可实现逻辑和存储器件的高性能，低电压（低功耗）操作。

    Abrupt junction formation by atomic layer epitaxy of in situ delta doped dopant diffusion barriers
    58.
    发明授权
    Abrupt junction formation by atomic layer epitaxy of in situ delta doped dopant diffusion barriers 有权
    通过原子层外延原位δ掺杂掺杂剂扩散阻挡层的突变结形成

    公开(公告)号：US07485536B2

    公开(公告)日：2009-02-03

    申请号：US11326178

    申请日：2005-12-30

    申请人： Been-Yih Jin ,  Brian S. Doyle ,  Robert S. Chau ,  Jack T. Kavalieros

    发明人： Been-Yih Jin ,  Brian S. Doyle ,  Robert S. Chau ,  Jack T. Kavalieros

    IPC分类号： H01L21/335

    CPC分类号： H01L29/0847 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7851

    摘要： A method including forming a channel region between source and drain regions in a substrate, the channel region including a first dopant profile; and forming a barrier layer between the channel region and a well of the substrate, the barrier layer including a second dopant profile different from the first dopant profile. An apparatus including a gate electrode on a substrate; source and drain regions formed in the substrate and separated by a channel region; and a barrier layer between a well of the substrate and the channel region, the barrier layer including a dopant profile different than a dopant profile of the channel region and different than a dopant profile of the well. A system including a computing device including a microprocessor, the microprocessor including a plurality of transistor devices formed in a substrate, each of the plurality of transistor devices including a gate electrode on the substrate; source and drain regions formed in the substrate and separated by a channel region; and a barrier layer between a well of the substrate and the channel region.

    摘要翻译： 一种方法，包括在衬底中的源区和漏区之间形成沟道区，所述沟道区包括第一掺杂物分布; 以及在所述沟道区和所述衬底的阱之间形成阻挡层，所述阻挡层包括不同于所述第一掺杂剂分布的第二掺杂剂分布。 一种在基板上包括栅电极的装置; 源极和漏极区域形成在衬底中并被沟道区域分离; 以及在衬底的阱和沟道区之间的阻挡层，阻挡层包括不同于沟道区的掺杂物分布并且不同于阱的掺杂剂分布的掺杂剂分布。 一种包括包括微处理器的计算设备的系统，所述微处理器包括形成在衬底中的多个晶体管器件，所述多个晶体管器件中的每一个在所述衬底上包括栅电极; 源极和漏极区域形成在衬底中并被沟道区域分离; 以及衬底的阱和沟道区之间的阻挡层。