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1.发明授权公开(公告)号：US07767560B2
公开(公告)日：2010-08-03
申请号：US11864963
申请日：2007-09-29
CPC分类号： H01L29/0665 , B82Y10/00 , H01L21/02381 , H01L21/0243 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/02664 , H01L29/0673 , H01L29/1054 , H01L29/66818 , H01L29/7851
摘要： The present disclosure describes a method and apparatus for implementing a 3D (three dimensional) strained high mobility quantum well structure, and a 3D strained surface channel structure through a Ge confinement method. One exemplary apparatus may include a first graded SiGe fin on a Si substrate. The first graded SiGe fin may have a maximum Ge concentration greater than about 60%. A Ge quantum well may be on the first graded SiGe fin and a SiGe quantum well upper barrier layer may be on the Ge quantum well. The exemplary apparatus may further include a second graded SiGe fin on the Si substrate. The second graded SiGe fin may have a maximum Ge concentration less than about 40%. A Si active channel layer may be on the second graded SiGe fin. Other high mobility materials such as III-V semiconductors may be used as the active channel materials. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
摘要翻译： 本公开描述了通过Ge约束法实现3D（三维）应变高迁移量子阱结构和3D应变表面通道结构的方法和装置。 一个示例性设备可以包括在Si衬底上的第一梯度SiGe鳍。 第一级的SiGe鳍可以具有大于约60％的最大Ge浓度。 Ge量子阱可以在第一等级的SiGe鳍上，SiGe量子阱上阻挡层可以在Ge量子阱上。 示例性设备还可以包括在Si衬底上的第二渐变SiGe鳍。 第二级的SiGe鳍可以具有小于约40％的最大Ge浓度。 Si活性沟道层可以在第二级别的SiGe鳍上。 可以使用诸如III-V族半导体的其它高迁移率材料作为活性通道材料。 当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。
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2.发明申请SILICON GERMANIUM AND GERMANIUM MULTIGATE AND NANOWIRE STRUCTURES FOR LOGIC AND MULTILEVEL MEMORY APPLICATIONS 审中-公开硅锗和锗多晶硅和纳米结构用于逻辑和多种存储器应用公开(公告)号：US20140170817A1
公开(公告)日：2014-06-19
申请号：US14184999
申请日：2014-02-20
CPC分类号： H01L21/02381 , B82Y10/00 , H01L21/02164 , H01L21/02236 , H01L21/0245 , H01L21/02507 , H01L21/02532 , H01L21/02603 , H01L21/30604 , H01L21/31658 , H01L21/76283 , H01L21/823807 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/068 , H01L29/1054 , H01L29/165 , H01L29/42324 , H01L29/42392 , H01L29/66439 , H01L29/66795 , H01L29/66818 , H01L29/775 , H01L29/785 , H01L29/78696
摘要： A method to provide a transistor or memory cell structure. The method comprises: providing a substrate including a lower Si substrate and an insulating layer on the substrate; providing a first projection extending above the insulating layer, the first projection including an Si material and a Sil-xGex material; and exposing the first projection to preferential oxidation to yield a second projection including a center region comprising Ge/Sil-yGey and a covering region comprising SiO2 and enclosing the center region.
摘要翻译： 一种提供晶体管或存储单元结构的方法。 该方法包括：在衬底上提供包括下Si衬底和绝缘层的衬底; 提供在所述绝缘层上方延伸的第一突起，所述第一突起包括Si材料和Sil-xGex材料; 以及将所述第一突起暴露于优先氧化以产生包括包含Ge / Sil-yGey的中心区域和包含SiO 2并包围所述中心区域的覆盖区域的第二突出部。
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3.发明申请公开(公告)号：US20090085027A1
公开(公告)日：2009-04-02
申请号：US11864963
申请日：2007-09-29
IPC分类号： H01L29/12 , H01L21/205
CPC分类号： H01L29/0665 , B82Y10/00 , H01L21/02381 , H01L21/0243 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/02664 , H01L29/0673 , H01L29/1054 , H01L29/66818 , H01L29/7851
摘要： The present disclosure describes a method and apparatus for implementing a 3D (three dimensional) strained high mobility quantum well structure, and a 3D strained surface channel structure through a Ge confinement method. One exemplary apparatus may include a first graded SiGe fin on a Si substrate. The first graded SiGe fin may have a maximum Ge concentration greater than about 60%. A Ge quantum well may be on the first graded SiGe fin and a SiGe quantum well upper barrier layer may be on the Ge quantum well. The exemplary apparatus may further include a second graded SiGe fin on the Si substrate. The second graded SiGe fin may have a maximum Ge concentration less than about 40%. A Si active channel layer may be on the second graded SiGe fin. Other high mobility materials such as III-V semiconductors may be used as the active channel materials. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
摘要翻译： 本公开描述了通过Ge约束法实现3D（三维）应变高迁移量子阱结构和3D应变表面通道结构的方法和装置。 一个示例性设备可以包括在Si衬底上的第一梯度SiGe鳍。 第一级的SiGe鳍可以具有大于约60％的最大Ge浓度。 Ge量子阱可以在第一等级的SiGe鳍上，SiGe量子阱上阻挡层可以在Ge量子阱上。 示例性设备还可以包括在Si衬底上的第二渐变SiGe鳍。 第二级的SiGe鳍可以具有小于约40％的最大Ge浓度。 Si活性沟道层可以在第二级别的SiGe鳍上。 可以使用诸如III-V族半导体的其它高迁移率材料作为活性通道材料。 当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。
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公开(公告)号：US07138316B2
公开(公告)日：2006-11-21
申请号：US10669064
申请日：2003-09-23
申请人： Been-Yih Jin , Brian S. Doyle , Scott A. Hareland , Mark L. Doczy , Matthew V. Metz , Boyan I. Boyanov , Suman Datta , Jack T. Kavalieros , Robert S. Chau
发明人： Been-Yih Jin , Brian S. Doyle , Scott A. Hareland , Mark L. Doczy , Matthew V. Metz , Boyan I. Boyanov , Suman Datta , Jack T. Kavalieros , Robert S. Chau
IPC分类号： H01L21/336
CPC分类号： H01L29/66772 , H01L21/02381 , H01L21/0245 , H01L21/02463 , H01L21/02466 , H01L21/02532 , H01L21/02546 , H01L21/02549 , H01L21/02639 , H01L21/02647 , H01L21/02664 , H01L21/76877 , H01L21/76879 , H01L21/76886 , H01L29/66742 , H01L29/78603 , H01L29/78648 , H01L29/78681
摘要： A method including forming a via dielectric layer on a semiconductor device substrate; forming a trench dielectric layer on the via dielectric layer; forming a trench through the trench dielectric layer to expose the via dielectric layer; forming a via in the via dielectric layer through the trench to expose the substrate; and forming a semiconductor material in the via and in the trench. An apparatus including a device substrate; a dielectric layer formed on a surface of the device substrate; and a device base formed on the dielectric layer including a crystalline structure derived from the device substrate.
摘要翻译： 一种包括在半导体器件基板上形成通孔电介质层的方法; 在所述通孔电介质层上形成沟槽电介质层; 通过所述沟槽电介质层形成沟槽以暴露所述通孔电介质层; 在所述通孔电介质层中通过所述沟槽形成通孔以暴露所述衬底; 以及在通孔和沟槽中形成半导体材料。 一种装置，包括：装置基板; 形成在所述器件基板的表面上的电介质层; 以及形成在所述电介质层上的器件基底，其包括衍生自所述器件基板的晶体结构。
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5.发明申请CMOS DEVICES WITH A SINGLE WORK FUNCTION GATE ELECTRODE AND METHOD OF FABRICATION 有权具有单个工作功能门电极的CMOS器件及其制造方法公开(公告)号：US20110180851A1
公开(公告)日：2011-07-28
申请号：US13038190
申请日：2011-03-01
申请人： Brian S. Doyle , Been-Yih Jin , Jack T. Kavalieros , Suman Datta , Justin K. Brask , Robert S. Chau
发明人： Brian S. Doyle , Been-Yih Jin , Jack T. Kavalieros , Suman Datta , Justin K. Brask , Robert S. Chau
IPC分类号： H01L29/772
CPC分类号： H01L21/845 , H01L21/823807 , H01L21/823821 , H01L21/823878 , H01L27/1211 , H01L29/0673 , H01L29/068 , H01L29/1054 , H01L29/66439 , H01L29/66795 , H01L29/775 , H01L29/785
摘要： Described herein are a device utilizing a gate electrode material with a single work function for both the pMOS and nMOS transistors where the magnitude of the transistor threshold voltages is modified by semiconductor band engineering and article made thereby. Further described herein are methods of fabricating a device formed of complementary (pMOS and nMOS) transistors having semiconductor channel regions which have been band gap engineered to achieve a low threshold voltage.
摘要翻译： 这里描述了利用具有单功函数的栅电极材料的器件，用于pMOS和nMOS晶体管，其中晶体管阈值电压的幅度由半导体带工程和由此制成的制品修改。 本文进一步描述的是制造由互补（pMOS和nMOS）晶体管形成的器件的方法，该晶体管具有被设计成能够实现低阈值电压的带隙的半导体沟道区。
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6.发明申请Silicon germanium and germanium multigate and nanowire structures for logic and multilevel memory applications 有权用于逻辑和多级存储器应用的硅锗和锗多重和纳米线结构公开(公告)号：US20080237575A1
公开(公告)日：2008-10-02
申请号：US11729565
申请日：2007-03-29
IPC分类号： H01L29/15 , H01L21/335
CPC分类号： H01L21/02381 , B82Y10/00 , H01L21/02164 , H01L21/02236 , H01L21/0245 , H01L21/02507 , H01L21/02532 , H01L21/02603 , H01L21/30604 , H01L21/31658 , H01L21/76283 , H01L21/823807 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/068 , H01L29/1054 , H01L29/165 , H01L29/42324 , H01L29/42392 , H01L29/66439 , H01L29/66795 , H01L29/66818 , H01L29/775 , H01L29/785 , H01L29/78696
摘要： A method to provide a transistor or memory cell structure. The method comprises: providing a substrate including a lower Si substrate and an insulating layer on the substrate; providing a first projection extending above the insulating layer, the first projection including an Si material and a Si1-xGex material; and exposing the first projection to preferential oxidation to yield a second projection including a center region comprising Ge/Si1-yGey and a covering region comprising SiO2 and enclosing the center region.
摘要翻译： 一种提供晶体管或存储单元结构的方法。 该方法包括：在衬底上提供包括下Si衬底和绝缘层的衬底; 提供在所述绝缘层上方延伸的第一突起，所述第一突起包括Si材料和Si1-xGex材料; 以及将所述第一突起暴露于优先氧化以产生包括包含Ge / Si1-yGey的中心区域和包含SiO 2并包围所述中心区域的覆盖区域的第二突起。
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7.发明授权CMOS devices with a single work function gate electrode and method of fabrication 有权CMOS器件具有单功能功能的栅电极和制造方法公开(公告)号：US08294180B2
公开(公告)日：2012-10-23
申请号：US13038190
申请日：2011-03-01
申请人： Brian S. Doyle , Been-Yih Jin , Jack T. Kavalieros , Suman Datta , Justin K. Brask , Robert S. Chau
发明人： Brian S. Doyle , Been-Yih Jin , Jack T. Kavalieros , Suman Datta , Justin K. Brask , Robert S. Chau
IPC分类号： H01L29/66
CPC分类号： H01L21/845 , H01L21/823807 , H01L21/823821 , H01L21/823878 , H01L27/1211 , H01L29/0673 , H01L29/068 , H01L29/1054 , H01L29/66439 , H01L29/66795 , H01L29/775 , H01L29/785
摘要： Described herein are a device utilizing a gate electrode material with a single work function for both the pMOS and nMOS transistors where the magnitude of the transistor threshold voltages is modified by semiconductor band engineering and article made thereby. Further described herein are methods of fabricating a device formed of complementary (pMOS and nMOS) transistors having semiconductor channel regions which have been band gap engineered to achieve a low threshold voltage.
摘要翻译： 这里描述了利用具有单功函数的栅电极材料的器件，用于pMOS和nMOS晶体管，其中晶体管阈值电压的幅度由半导体带工程和由此制成的制品修改。 本文进一步描述的是制造由互补（pMOS和nMOS）晶体管形成的器件的方法，该晶体管具有被设计成能够实现低阈值电压的带隙的半导体沟道区。
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8.发明授权CMOS devices with a single work function gate electrode and method of fabrication 有权CMOS器件具有单功能功能的栅电极和制造方法公开(公告)号：US07902014B2
公开(公告)日：2011-03-08
申请号：US11649545
申请日：2007-01-03
申请人： Brian S. Doyle , Been-Yih Jin , Jack T. Kavalieros , Suman Datta , Justin K. Brask , Robert S. Chau
发明人： Brian S. Doyle , Been-Yih Jin , Jack T. Kavalieros , Suman Datta , Justin K. Brask , Robert S. Chau
IPC分类号： H01L21/8234
CPC分类号： H01L21/845 , H01L21/823807 , H01L21/823821 , H01L21/823878 , H01L27/1211 , H01L29/0673 , H01L29/068 , H01L29/1054 , H01L29/66439 , H01L29/66795 , H01L29/775 , H01L29/785
摘要： Described herein are a device utilizing a gate electrode material with a single work function for both the pMOS and nMOS transistors where the magnitude of the transistor threshold voltages is modified by semiconductor band engineering and article made thereby. Further described herein are methods of fabricating a device formed of complementary (pMOS and nMOS) transistors having semiconductor channel regions which have been band gap engineered to achieve a low threshold voltage.
摘要翻译： 这里描述了利用具有单功函数的栅电极材料的器件，用于pMOS和nMOS晶体管，其中晶体管阈值电压的幅度由半导体带工程和由此制成的制品修改。 本文进一步描述的是制造由互补（pMOS和nMOS）晶体管形成的器件的方法，该晶体管具有被设计成能够实现低阈值电压的带隙的半导体沟道区。
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9.发明申请SILICON GERMANIUM AND GERMANIUM MULTIGATE AND NANOWIRE STRUCTURES FOR LOGIC AND MULTILEVEL MEMORY APPLICATIONS 失效硅锗和锗多晶硅和纳米结构用于逻辑和多种存储器应用公开(公告)号：US20110008937A1
公开(公告)日：2011-01-13
申请号：US12885071
申请日：2010-09-17
IPC分类号： H01L21/84
CPC分类号： H01L21/02381 , B82Y10/00 , H01L21/02164 , H01L21/02236 , H01L21/0245 , H01L21/02507 , H01L21/02532 , H01L21/02603 , H01L21/30604 , H01L21/31658 , H01L21/76283 , H01L21/823807 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/068 , H01L29/1054 , H01L29/165 , H01L29/42324 , H01L29/42392 , H01L29/66439 , H01L29/66795 , H01L29/66818 , H01L29/775 , H01L29/785 , H01L29/78696
摘要： A method to provide a transistor or memory cell structure. The method comprises: providing a substrate including a lower Si substrate and an insulating layer on the substrate; providing a first projection extending above the insulating layer, the first projection including an Si material and a Si1-xGex material; and exposing the first projection to preferential oxidation to yield a second projection including a center region comprising Ge/Si1-yGey and a covering region comprising SiO2 and enclosing the center region.
摘要翻译： 一种提供晶体管或存储单元结构的方法。 该方法包括：在衬底上提供包括下Si衬底和绝缘层的衬底; 提供在所述绝缘层上方延伸的第一突起，所述第一突起包括Si材料和Si1-xGex材料; 以及将所述第一突起暴露于优先氧化以产生包括包含Ge / Si1-yGey的中心区域和包含SiO 2并包围所述中心区域的覆盖区域的第二突起。
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公开(公告)号：US20090001441A1
公开(公告)日：2009-01-01
申请号：US11823758
申请日：2007-06-28
IPC分类号： H01L21/336 , H01L29/788
CPC分类号： H01L29/127 , B82Y10/00 , H01L21/8221 , H01L27/0688 , H01L27/115 , H01L27/11517 , H01L29/40114 , H01L29/42332
摘要： In one embodiment of the invention, oxidation of silicon in a silicon germanium/silicon lattice may convert a two dimensional array of silicon germanium pillars into a structured three dimensional quantum dot array. The array may be included in, for example, flash memory floating gate, optical detector, or quantum computing device.
摘要翻译： 在本发明的一个实施例中，硅锗/硅晶格中的硅的氧化可以将硅锗柱的二维阵列转换成结构化的三维量子点阵列。 阵列可以包括在例如闪存浮动栅极，光学检测器或量子计算设备中。
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