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公开(公告)号：US20230069721A1
公开(公告)日：2023-03-02
申请号：US17460070
申请日：2021-08-27
IPC分类号： G11C11/419 , G11C11/412 , H01L27/11
摘要： A memory device includes a memory array having a plurality of memory cells arranged along a plurality of rows extending in a row direction and a plurality of columns extending in a column direction. The memory array also includes a plurality of write assist cells connected to the plurality of memory cells. At least one write assist cell of the plurality of write assist cells is in each of the plurality of columns and connected to respective ones of the plurality of memory cells in a same column.
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公开(公告)号：US11538507B1
公开(公告)日：2022-12-27
申请号：US17461210
申请日：2021-08-30
摘要： Disclosed herein are related to an integrated circuit including a semiconductor layer. In one aspect, the semiconductor layer includes a first region, a second region, and a third region. The first region may include a circuit array, and the second region may include a set of interface circuits to operate the circuit array. A side of the first region may face a first side of the second region along a first direction. The third region may include a set of header circuits to provide power to the set of interface circuits through metal rails extending along a second direction. A side of the third region may face a second side of the second region along the second direction. In one aspect, the first side extending along the second direction is shorter than the second side extending along the first direction, and the metal rails are shorter than the first side.
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公开(公告)号：US20220359001A1
公开(公告)日：2022-11-10
申请号：US17814700
申请日：2022-07-25
IPC分类号： G11C11/419 , G11C11/418
摘要： A twelve-transistor (12T) memory cell for a memory device that includes a transmission gate, a cross-coupled inverter circuit operably connected to the transmission gate, and a tri-state inverter operably connected to the cross-coupled inverter circuit. The cross-coupled inverter includes another tri-state inverter cross-coupled to an inverter circuit. Various operations for the 12T memory cell, as well as circuitry to perform the operations, are disclosed.
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54.发明申请公开(公告)号：US20210306148A1
公开(公告)日：2021-09-30
申请号：US17106856
申请日：2020-11-30
发明人： Shih-Lien Linus Lu , Kun-hsi Li , Shih-Liang Wang , Jonathan Tsung-Yung Chang , Yu-Der Chih , Cheng-En Lee
摘要： Systems and methods of generating a security key for an integrated circuit device include generating a plurality of key bits with a physically unclonable function (PUF) device. The PUF can include a random number generator that can create random bits. The random bits may be stored in a nonvolatile memory. The number of random bits stored in the nonvolatile memory allows for a plurality of challenge and response interactions to obtain a plurality of security keys from the PUF.
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55.发明授权公开(公告)号：US10991420B2
公开(公告)日：2021-04-27
申请号：US16991449
申请日：2020-08-12
IPC分类号： G11C11/4094 , G11C7/12 , G11C11/4096
摘要： A semiconductor memory device includes: a column of segments, each segment including bit cells; a local write bit (LWB) line; a local write bit_bar (LWB_bar) line; a global write bit (GWB) line; a global write bit_bar (GWBL_bar) line; each of the bit cells being connected correspondingly between the LWB and LWB_bar lines; and a distributed write driving arrangement including a global write driver connected between the GWB line and the LWB line and between the GWB_bar line and the LWB_bar line; and a local write driver included in each segment, each local write driver being connected between the GWB line and the LWB line and between the GWB_bar line and the LWB_bar line; and wherein: the global write driver and each local write driver is connected between the GWB line and the LWB line and between the GWB_bar line and the LWB_bar line.
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56.发明授权公开(公告)号：US10553275B2
公开(公告)日：2020-02-04
申请号：US15949774
申请日：2018-04-10
IPC分类号： G11C11/00 , G11C11/419 , G06F17/50 , H01L27/11 , G03F1/32 , G03F1/20 , G03F1/26 , G03F1/30 , G03F1/36
摘要： A write assist circuit includes: a memory-adapted latch and memory-adapted third and fourth NMOS transistors. The latch includes: a memory-adapted first PMOS transistor and a memory-adapted first NMOS transistor connected in series between a power-supply voltage and a first node, the first node being selectively connectable to a ground voltage; and a memory-adapted second PMOS transistor and a memory-adapted second NMOS transistor connected in series between the power-supply voltage and the second node, the second node being selectively connectable to the ground voltage. The third NMOS transistor is connected in series between the first node and the ground voltage; and the fourth NMOS transistor connected in series between the second node and the ground voltage. A gate electrode of each of the third and fourth transistors is connected to a latch-enable signal-line thereby for controlling the memory-adapted latch.
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公开(公告)号：US20190385672A1
公开(公告)日：2019-12-19
申请号：US16415554
申请日：2019-05-17
IPC分类号： G11C11/419 , G11C11/418
摘要： A twelve-transistor (12T) memory cell for a memory device that includes a transmission gate, a cross-coupled inverter circuit operably connected to the transmission gate, and a tri-state inverter operably connected to the cross-coupled inverter circuit. The cross-coupled inverter includes another tri-state inverter cross-coupled to an inverter circuit. Various operations for the 12T memory cell, as well as circuitry to perform the operations, are disclosed.
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58.发明授权公开(公告)号：US10268787B2
公开(公告)日：2019-04-23
申请号：US15651714
申请日：2017-07-17
IPC分类号： G06F17/50
摘要： A hybrid timing analysis method includes: receiving a pre-layout netlist, a post-layout netlist and a configuration file associated with an integrated circuit design; generating a first measurement script and an input stimulus waveform file according to the configuration file; performing a first dynamic timing analysis upon the pre-layout netlist by using the first measurement script and the input stimulus waveform file to generate a pre-layout simulation result; identifying at least one data path and at least one clock path according to the pre-layout simulation result; generating a second measurement script according to the at least on data path and at least one clock path; and performing a second dynamic timing analysis upon the post-layout netlist by using the second measurement script and the input stimulus waveform file to generate a first post-layout simulation result. Associated system and non-transitory computer readable medium are also provided.
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公开(公告)号：US09959916B2
公开(公告)日：2018-05-01
申请号：US15589313
申请日：2017-05-08
IPC分类号： G11C7/00 , G11C7/12 , G11C5/14 , G11C7/10 , G11C7/06 , G11C7/22 , G11C8/10 , G11C8/06 , G11C8/08 , G11C11/418 , G11C11/417
CPC分类号： G11C7/12 , G11C5/14 , G11C5/147 , G11C7/06 , G11C7/065 , G11C7/10 , G11C7/22 , G11C8/06 , G11C8/08 , G11C8/10 , G11C11/417 , G11C11/418
摘要： A dual rail memory operable at a first voltage and a second voltage, the dual rail memory includes: a memory array operates at the first voltage; a word line driver circuit configured to drive a word line of the memory array to the first voltage; a data path configured to transmit an input data signal or an output data signal; and a control circuit configured to generate control signals to the memory array, the word line driver circuit and the data path; wherein the data path and the control circuit are configured to operate at both the first and second voltages. Associated memory macro and method are also disclosed.
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公开(公告)号：US09824729B2
公开(公告)日：2017-11-21
申请号：US15434541
申请日：2017-02-16
发明人： Chien-Kuo Su , Cheng Hung Lee , Chiting Cheng , Hung-Jen Liao , Jonathan Tsung-Yung Chang , Yen-Huei Chen , Pankaj Aggarwal , Jhon Jhy Liaw
CPC分类号： G11C7/12 , G11C7/227 , G11C11/419
摘要： A memory macro includes a first memory cell array, a first tracking circuit and a first pre-charge circuit. The first tracking circuit includes a first set of memory cells configured as a first set of loading cells responsive to a first set of control signals, a second set of memory cells configured as a first set of pull-down cells responsive to a second set of control signals, and a first tracking bit line coupled to the first set of memory cells and the second set of memory cells. The first set of pull-down cells and the first set of loading cells are configured to track a memory cell of the first memory cell array. The first pre-charge circuit is coupled to the first tracking bit line, and is configured to charge the first tracking bit line to a pre-charge voltage level responsive to a third set of control signals.
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