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    EMBEDDED DIE PACKAGING WITH INTEGRATED CERAMIC SUBSTRATE
    52.
    发明申请
    EMBEDDED DIE PACKAGING WITH INTEGRATED CERAMIC SUBSTRATE 有权

    公开(公告)号：US20220108955A1

    公开(公告)日：2022-04-07

    申请号：US17517608

    申请日：2021-11-02

    Applicant: Texas Instruments Incorporated

    Inventor： Woochan Kim ,  Mutsumi Masumoto ,  Kengo Aoya ,  Vivek Kishorechand Arora ,  Anindya Poddar

    IPC: H01L23/538 ,  H01L23/498 ,  H01L21/56 ,  H01L23/373

    Abstract: Packaged electronic devices and integrated circuits include a ceramic material or other thermally conductive, electrically insulating substrate with a patterned electrically conductive feature on a first side, and an electrically conductive layer on a second side. The IC further includes a semiconductor die mounted to the substrate, the semiconductor die including an electrically conductive contact structure, and an electronic component, with an electrically insulating lamination structure enclosing the semiconductor die, the frame and the thermal transfer structure. A redistribution layer with a conductive structure is electrically connected to the electrically conductive contact structure.

    EMBEDDED DIE PACKAGING WITH INTEGRATED CERAMIC SUBSTRATE
    55.
    发明申请
    EMBEDDED DIE PACKAGING WITH INTEGRATED CERAMIC SUBSTRATE 审中-公开

    公开(公告)号：US20200091076A1

    公开(公告)日：2020-03-19

    申请号：US16132906

    申请日：2018-09-17

    Applicant: Texas Instruments Incorporated

    Inventor： Woochan Kim ,  Mutsumi Masumoto ,  Kengo Aoya ,  Vivek Kishorechand Arora ,  Anindya Poddar

    IPC: H01L23/538 ,  H01L23/373 ,  H01L21/56 ,  H01L23/498

    Abstract: Packaged electronic devices and integrated circuits include a ceramic material or other thermally conductive, electrically insulating substrate with a patterned electrically conductive feature on a first side, and an electrically conductive layer on a second side. The IC further includes a semiconductor die mounted to the substrate, the semiconductor die including an electrically conductive contact structure, and an electronic component, with an electrically insulating lamination structure enclosing the semiconductor die, the frame and the thermal transfer structure. A redistribution layer with a conductive structure is electrically connected to the electrically conductive contact structure.

    Stress buffer layer in embedded package
    57.
    发明授权
    Stress buffer layer in embedded package 有权

    公开(公告)号：US10580715B2

    公开(公告)日：2020-03-03

    申请号：US16008119

    申请日：2018-06-14

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Woochan Kim ,  Masamitsu Matsuura ,  Mutsumi Masumoto ,  Kengo Aoya ,  Hau Thanh Nguyen ,  Vivek Kishorechand Arora ,  Anindya Poddar

    IPC: H01L23/10 ,  H01L23/34 ,  H01L23/367 ,  H01L21/56 ,  H01L23/00 ,  H01L23/373

    Abstract: The disclosed principles provide a stress buffer layer between an IC die and heat spreader used to dissipate heat from the die. The stress buffer layer comprises distributed pairs of conductive pads and a corresponding set of conductive posts formed on the conductive pads. In one embodiment, the stress buffer layer may comprise conductive pads laterally distributed over non-electrically conducting surfaces of an embedded IC die to thermally conduct heat from the IC die. In addition, such a stress buffer layer may comprise conductive posts laterally distributed and formed directly on each of the conductive pads. Each of the conductive posts thermally conduct heat from respective conductive pads. In addition, each conductive post may have a lateral width less than a lateral width of its corresponding conductive pad. A heat spreader is then formed over the conductive posts which thermally conducts heat from the conductive posts through the heat spreader.

    FORMING INTEGRATED INDUCTORS AND TRANSFORMERS WITH EMBEDDED MAGNETIC CORES
    59.
    发明申请
    FORMING INTEGRATED INDUCTORS AND TRANSFORMERS WITH EMBEDDED MAGNETIC CORES 审中-公开
    形成集成电感器和带有嵌入式磁性线的变压器

    公开(公告)号：US20150143690A1

    公开(公告)日：2015-05-28

    申请号：US14549746

    申请日：2014-11-21

    Applicant: Texas Instruments Incorporated

    Inventor： Anindya Poddar

    IPC: H01F41/14

    CPC classification number: H01F41/046 ,  Y10T29/49073

    Abstract: In accordance with an embodiment of the application a method of forming an integrated magnetic device is described. A prepreg or core is mounted on a carrier. A winding layer is plated and patterned on the prepreg or core. Vias are plated. The silicon is placed on a die attach pad, ensuring sufficient clearance of die to vias and d/a char. The assembly is laminated and grinded to expose the vias. A 2nd layer of vias is provided by sputtering or plating followed by laminating assembly; and grinding assembly to expose vias. The windings are plated and patterned. A solder mask (SMSK) is applied and assembly finished.

    Abstract translation: 根据本申请的实施例，描述了形成集成磁性装置的方法。 预浸料或芯体安装在载体上。 卷绕层被镀覆并在预浸料或芯上图案化。 通孔是电镀的。 将硅放置在管芯附着垫上，确保裸片与通孔和d / a炭的充分间隙。 将组件层压并研磨以暴露通孔。 通过溅射或电镀，然后层压组件提供第二层通孔; 和磨削组件暴露通孔。 绕组被电镀和图案化。 焊接面罩（SMSK）被应用并组装完成。

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