公开(公告)号：US20230013270A1

公开(公告)日：2023-01-19

申请号：US17956136

申请日：2022-09-29

Applicant: Texas Instruments Incorporated

Inventor： Abhijeet Ashok Chachad ,  Timothy David Anderson ,  David Matthew Thompson ,  Daniel Brad Wu

IPC: G06F11/10 ,  G06F3/06 ,  G06F12/0811 ,  G06F9/38 ,  G06F12/0815 ,  G06F12/126

Abstract: In described examples, a processor system includes a processor core that generates memory write requests, and a cache memory with a memory controller having a memory pipeline. The cache memory has cache lines of length L. The cache memory has a minimum write length that is less than a cache line length of the cache memory. The memory pipeline determines whether the data payload includes a first chunk and ECC syndrome that correspond to a partial write and are writable by a first cache write operation, and a second chunk and ECC syndrome that correspond to a full write operation that can be performed separately from the first cache write operation. The memory pipeline performs an RMW operation to store the first chunk and ECC syndrome in the cache memory, and performs the full write operation to store the second chunk and ECC syndrome in the cache memory.

公开(公告)号：US11461127B2

公开(公告)日：2022-10-04

申请号：US16882321

申请日：2020-05-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abhijeet Ashok Chachad ,  David Matthew Thompson

IPC: G06F9/46 ,  G06F9/48 ,  G06F9/448 ,  G06F9/38 ,  G06F9/54 ,  G06F12/0811 ,  G06F11/30 ,  G06F12/0813 ,  G06F12/0817 ,  G06F9/30 ,  G06F12/0871 ,  G06F12/0891 ,  G06F12/12 ,  G06F13/16 ,  G06F12/0888 ,  G06F12/0831 ,  G06F12/0855 ,  G06F12/0804 ,  G06F12/121

Abstract: A method includes receiving, by a first stage in a pipeline, a first transaction from a previous stage in pipeline; in response to first transaction comprising a high priority transaction, processing high priority transaction by sending high priority transaction to a buffer; receiving a second transaction from previous stage; in response to second transaction comprising a low priority transaction, processing low priority transaction by monitoring a full signal from buffer while sending low priority transaction to buffer; in response to full signal asserted and no high priority transaction being available from previous stage, pausing processing of low priority transaction; in response to full signal asserted and a high priority transaction being available from previous stage, stopping processing of low priority transaction and processing high priority transaction; and in response to full signal being de-asserted, processing low priority transaction by sending low priority transaction to buffer.

公开(公告)号：US11294707B2

公开(公告)日：2022-04-05

申请号：US16882365

申请日：2020-05-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abhijeet Ashok Chachad ,  Naveen Bhoria ,  David Matthew Thompson ,  Neelima Muralidharan

IPC: G06F9/46 ,  G06F9/48 ,  G06F9/448 ,  G06F11/30 ,  G06F9/54 ,  G06F12/0811 ,  G06F9/38 ,  G06F12/0813 ,  G06F12/0817 ,  G06F9/30 ,  G06F12/0871 ,  G06F12/0891 ,  G06F12/12 ,  G06F13/16 ,  G06F12/0888 ,  G06F12/0831 ,  G06F12/0855 ,  G06F12/0804 ,  G06F12/121

Abstract: A method includes receiving, by a L2 controller, a request to perform a global operation on a L2 cache and preventing new blocking transactions from entering a pipeline coupled to the L2 cache while permitting new non-blocking transactions to enter the pipeline. Blocking transactions include read transactions and non-victim write transactions. Non-blocking transactions include response transactions, snoop transactions, and victim transactions. The method further includes, in response to an indication that the pipeline does not contain any pending blocking transactions, preventing new snoop transactions from entering the pipeline while permitting new response transactions and victim transactions to enter the pipeline; in response to an indication that the pipeline does not contain any pending snoop transactions, preventing, all new transactions from entering the pipeline; and, in response to an indication that the pipeline does not contain any pending transactions, performing the global operation on the L2 cache.

公开(公告)号：US20220058127A1

公开(公告)日：2022-02-24

申请号：US17520805

申请日：2021-11-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Bipin Prasad Heremagalur Ramaprasad ,  David Matthew Thompson ,  Abhijeet Ashok Chachad ,  Hung ONG

IPC: G06F12/0862 ,  G06F9/38 ,  G06F12/0811

Abstract: An apparatus includes a CPU core, a first memory cache with a first line size, and a second memory cache having a second line size larger than the first line size. Each line of the second memory cache includes an upper half and a lower half. A memory controller subsystem is coupled to the CPU core and to the first and second memory caches. Upon a miss in the first memory cache for a first target address, the memory controller subsystem determines that the first target address resulting in the miss maps to the lower half of a line in the second memory cache, retrieves the entire line from the second memory cache, and returns the entire line from the second memory cache to the first memory cache.

公开(公告)号：US11237905B2

公开(公告)日：2022-02-01

申请号：US16874435

申请日：2020-05-14

Applicant: Texas Instruments Incorporated

Inventor： Abhijeet Ashok Chachad ,  David Matthew Thompson ,  Daniel Brad Wu

IPC: G06F11/10 ,  G06F3/06 ,  G06F12/0811 ,  G06F9/38 ,  G06F12/0815 ,  G06F12/126

Abstract: In described examples, a processor system includes a processor core that generates memory write requests, a cache memory, and a memory pipeline of the cache memory. The memory pipeline has a holding buffer, an anchor stage, and an RMW pipeline. The anchor stage determines whether a data payload of a write request corresponds to a partial write. If so, the data payload is written to the holding buffer and conforming data is read from a corresponding cache memory address to merge with the data payload. The RMW pipeline has a merge stage and a syndrome generation stage. The merge stage merges the data payload in the holding buffer with the conforming data to make merged data. The syndrome generation stage generates an ECC syndrome using the merged data. The memory pipeline writes the data payload and ECC syndrome to the cache memory.

公开(公告)号：US20220027275A1

公开(公告)日：2022-01-27

申请号：US17492776

申请日：2021-10-04

Applicant: Texas Instruments Incorporated

Inventor： Abhijeet Ashok Chachad ,  Timothy David Anderson ,  Kai Chirca ,  David Matthew Thompson

IPC: G06F12/0842 ,  G06F12/0811 ,  G06F12/0888 ,  G06F1/14 ,  G06F9/54

Abstract: In described examples, a processor system includes a processor core generating memory transactions, a lower level cache memory with a lower memory controller, and a higher level cache memory with a higher memory controller having a memory pipeline. The higher memory controller is connected to the lower memory controller by a bypass path that skips the memory pipeline. The higher memory controller: determines whether a memory transaction is a bypass write, which is a memory write request indicated not to result in a corresponding write being directed to the higher level cache memory; if the memory transaction is determined a bypass write, determines whether a memory transaction that prevents passing is in the memory pipeline; and if no transaction that prevents passing is determined to be in the memory pipeline, sends the memory transaction to the lower memory controller using the bypass path.

公开(公告)号：US11138117B2

公开(公告)日：2021-10-05

申请号：US16879264

申请日：2020-05-20

Applicant: Texas Instruments Incorporated

Inventor： Abhijeet Ashok Chachad ,  Timothy David Anderson ,  Kai Chirca ,  David Matthew Thompson

IPC: G06F12/00 ,  G06F12/0842 ,  G06F12/0811 ,  G06F12/0888 ,  G06F1/14 ,  G06F9/54

Abstract: In described examples, a processor system includes a processor core generating memory transactions, a lower level cache memory with a lower memory controller, and a higher level cache memory with a higher memory controller having a memory pipeline. The higher memory controller is connected to the lower memory controller by a bypass path that skips the memory pipeline. The higher memory controller: determines whether a memory transaction is a bypass write, which is a memory write request indicated not to result in a corresponding write being directed to the higher level cache memory; if the memory transaction is determined a bypass write, determines whether a memory transaction that prevents passing is in the memory pipeline; and if no transaction that prevents passing is determined to be in the memory pipeline, sends the memory transaction to the lower memory controller using the bypass path.

公开(公告)号：US20200371917A1

公开(公告)日：2020-11-26

申请号：US16874331

申请日：2020-05-14

Applicant: Texas Instruments Incorporated

Inventor： Abhijeet Ashok Chachad ,  Timothy David Anderson ,  David Matthew Thompson

IPC: G06F12/0811 ,  G06F9/54 ,  G06F1/14

Abstract: In described examples, a processor system includes a processor core that generates memory write requests, a cache memory, and a memory controller. The memory controller has a memory pipeline. The memory controller is coupled to control the cache memory and communicatively coupled to the processor core. The memory controller is configured to receive the memory write requests from the processor core; schedule the memory write requests on the memory pipeline; and contemporaneously with scheduling respective ones of the memory write requests on the memory pipeline, send to the processor core a write acknowledgment confirming that writing of a data payload of the respective memory write request to the cache memory has completed.

公开(公告)号：US20200371877A1

公开(公告)日：2020-11-26

申请号：US16874435

申请日：2020-05-14

Applicant: Texas Instruments Incorporated

Inventor： Abhijeet Ashok Chachad ,  David Matthew Thompson ,  Daniel Brad Wu

IPC: G06F11/10 ,  G06F3/06 ,  G06F12/0811

Abstract: In described examples, a processor system includes a processor core that generates memory write requests, a cache memory, and a memory pipeline of the cache memory. The memory pipeline has a holding buffer, an anchor stage, and an RMW pipeline. The anchor stage determines whether a data payload of a write request corresponds to a partial write. If so, the data payload is written to the holding buffer and conforming data is read from a corresponding cache memory address to merge with the data payload. The RMW pipeline has a merge stage and a syndrome generation stage. The merge stage merges the data payload in the holding buffer with the conforming data to make merged data. The syndrome generation stage generates an ECC syndrome using the merged data. The memory pipeline writes the data payload and ECC syndrome to the cache memory.

公开(公告)号：US09268708B2

公开(公告)日：2016-02-23

申请号：US14637580

申请日：2015-03-04

Applicant: Texas Instruments Incorporated

Inventor： Raguram Damodaran ,  Abhijeet Ashok Chachad ,  Jonathan (Son) Hung Tran ,  David Matthew Thompson

IPC: G06F12/12 ,  G06F12/10 ,  G06F7/483 ,  G06F9/30 ,  H03M13/35 ,  H03M13/29 ,  G06F11/10 ,  G06F13/16 ,  G06F13/18 ,  H03K19/00 ,  G06F1/32 ,  H03K21/00 ,  G06F12/02 ,  G06F12/08 ,  G06F13/364

CPC classification number: G06F12/1081 ,  G06F1/3296 ,  G06F7/483 ,  G06F9/3012 ,  G06F11/1064 ,  G06F12/0246 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/12 ,  G06F13/1605 ,  G06F13/1652 ,  G06F13/1657 ,  G06F13/1663 ,  G06F13/18 ,  G06F13/364 ,  G06F2212/1021 ,  G06F2212/1032 ,  G06F2212/221 ,  G06F2212/2532 ,  G06F2212/283 ,  G06F2212/608 ,  H03K19/0016 ,  H03K21/00 ,  H03M13/2903 ,  H03M13/353 ,  Y02D10/124 ,  Y02D10/172 ,  Y02D50/20

Abstract: This invention assures cache coherence in a multi-level cache system upon eviction of a higher level cache line. A victim buffer stored data on evicted lines. On a DMA access that may be cached in the higher level cache the lower level cache sends a snoop write. The address of this snoop write is compared with the victim buffer. On a hit in the victim buffer the write completes in the victim buffer. When the victim data passes to the next cache level it is written into a second victim buffer to be retired when the data is committed to cache. DMA write addresses are compared to addresses in this second victim buffer. On a match the write takes place in the second victim buffer. On a failure to match the controller sends a snoop write.