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    METHOD OF FORMING A CMOS-BASED THERMOELECTRIC DEVICE
    51.
    发明申请
    METHOD OF FORMING A CMOS-BASED THERMOELECTRIC DEVICE 审中-公开
    形成基于CMOS的热电装置的方法

    公开(公告)号：US20160155925A1

    公开(公告)日：2016-06-02

    申请号：US14957314

    申请日：2015-12-02

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Henry Litzmann Edwards ,  Kenneth James Maggio ,  Toan Tran ,  Jihong Chen ,  Jeffrey R. Debord

    IPC: H01L35/34 ,  H01L27/16

    CPC classification number: H01L35/34 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/823878 ,  H01L27/0617 ,  H01L27/092 ,  H01L27/10876 ,  H01L27/16 ,  H01L29/34 ,  H01L35/04 ,  H01L37/00 ,  H01L2924/13091

    Abstract: An integrated circuit containing CMOS transistors and an embedded thermoelectric device may be formed by forming field oxide in isolation trenches to isolate the CMOS transistors and thermoelectric elements of the embedded thermoelectric device. N-type dopants are implanted into the substrate to provide at least 1×1018 cm−3 n-type dopants in n-type thermoelectric elements and the substrate under the field oxide between the n-type thermoelectric elements. P-type dopants are implanted into the substrate to provide at least 1×1018 cm−3 p-type dopants in p-type thermoelectric elements and the substrate under the field oxide between the p-type thermoelectric elements. The n-type dopants and p-type dopants may be implanted before the field oxide are formed, after the isolation trenches for the field oxide are formed and before dielectric material is formed in the isolation trenches, and/or after the field oxide is formed.

    Abstract translation: 可以通过在隔离沟槽中形成场氧化物来隔离嵌入式热电装置的CMOS晶体管和热电元件来形成包含CMOS晶体管和嵌入式热电装置的集成电路。 将N型掺杂剂注入到衬底中以在n型热电元件中提供至少1×1018cm-3n型掺杂剂和在n型热电元件之间的场氧化物下的衬底。 P型掺杂剂被注入到衬底中以在p型热电元件中提供至少1×1018cm-3p型掺杂剂，并且在p型热电元件之间的场氧化物之下提供衬底。 在形成场氧化物的隔离沟槽之后，在隔离沟槽中形成介电材料之前和/或在形成场氧化物之后，可以在形成场氧化物之前，注入n型掺杂剂和p型掺杂剂 。

    Photodiode employing surface grating to enhance sensitivity
    52.
    发明授权
    Photodiode employing surface grating to enhance sensitivity 有权
    光电二极管采用表面光栅增强灵敏度

    公开(公告)号：US09082905B2

    公开(公告)日：2015-07-14

    申请号：US13768037

    申请日：2013-02-15

    Applicant: Texas Instruments Incorporated

    Inventor： Henry Litzmann Edwards ,  Dimitar Trifonov Trifonov

    IPC: H01L31/062 ,  H01L31/0236 ,  H01L31/0216 ,  H01L31/0232 ,  H01L31/103

    CPC classification number: H01L31/02366 ,  H01L31/02161 ,  H01L31/02327 ,  H01L31/103

    Abstract: A semiconductor device contains a photodiode formed in a substrate of the semiconductor device. At a top surface of the substrate, over the photodiode, a surface grating of periodic field oxide in a periodic configuration and/or gate structures in a periodic configuration is formed. The field oxide may be formed using an STI process or a LOCOS process. A semiconductor device with a surface grating including both field oxide and gate structures has the gate structures over the semiconductor substrate, between the field oxide. The surface grating has a pitch length up to 3 microns. The surface grating covers at least half of the photodiode.

    Abstract translation: 半导体器件包含形成在半导体器件的衬底中的光电二极管。 在衬底的顶表面上，在光电二极管上，形成具有周期性构造的周期性场氧化物的表面光栅和/或周期性构造的/或栅极结构。 场氧化物可以使用STI工艺或LOCOS工艺形成。 具有包括场氧化物和栅极结构的表面光栅的半导体器件在半导体衬底之间具有位于场氧化物之间的栅极结构。 表面光栅具有高达3微米的间距长度。 表面光栅覆盖光电二极管的至少一半。

    PHOTODIODE WITH A DARK CURRENT SUPPRESSION JUNCTION
    53.
    发明申请
    PHOTODIODE WITH A DARK CURRENT SUPPRESSION JUNCTION 有权
    具有低电流抑制结的光电

    公开(公告)号：US20150145097A1

    公开(公告)日：2015-05-28

    申请号：US14552995

    申请日：2014-11-25

    Applicant: Texas Instruments Incorporated

    Inventor： Debarshi Basu ,  Henry Litzmann Edwards ,  Dimitar Trifonov Trifonov ,  Josh Du

    IPC: H01L31/11 ,  H01L31/02 ,  H01L31/18

    CPC classification number: H01L31/1105

    Abstract: This invention relates to field photodiodes based on PN junctions that suffer from dark current leakage. An NBL is added to prove a second PN junction with the anode. The second PN junction is reversed biased in order to remove dark current leakage. The present solution requires no additional masks or thin films steps relative to a conventional CMOS process flow.

    Abstract translation: 本发明涉及基于PN结的场致电二极管，其具有暗电流泄漏。 添加NBL以证明与阳极的第二PN结。 第二个PN结被反向偏置，以消除暗电流泄漏。 本解决方案不需要相对于常规CMOS工艺流程的附加掩模或薄膜步骤。

    LASER ANNEAL FORMED NANOSHEET LDMOS TRANSISTOR
    55.
    发明申请
    LASER ANNEAL FORMED NANOSHEET LDMOS TRANSISTOR 有权

    公开(公告)号：US20240413242A1

    公开(公告)日：2024-12-12

    申请号：US18429228

    申请日：2024-01-31

    Applicant: Texas Instruments Incorporated

    Inventor： Henry Litzmann Edwards ,  Brian Goodlin ,  Sujatha Sampath

    IPC: H01L29/78 ,  H01L29/06 ,  H01L29/16 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

    Abstract: A microelectronic device, e.g. an integrated circuit, includes first and second doped semiconductor regions over a semiconductor substrate. A semiconductor nanosheet layer is connected between the first and second semiconductor regions and has a bandgap greater than 1.5 eV. In some examples such a device is implemented as an LDMOS transistor. A method of forming the device includes forming a trench in a semiconductor substrate having a first conductivity type. A semiconductor nanosheet stack is formed within the trench, the stack including a semiconductor nanosheet layer and a sacrificial layer. Source and drain regions having an opposite second conductivity type are formed extending into the semiconductor nanosheet stack. The sacrificial layer between the source region and the drain region is removed, and the semiconductor nanosheet layer is annealed. A gate dielectric layer is formed on the semiconductor nanosheet layer, and a gate conductor is formed on the gate dielectric layer.

    RUGGED LDMOS WITH FIELD PLATE
    60.
    发明公开
    RUGGED LDMOS WITH FIELD PLATE 审中-公开

    公开(公告)号：US20230317846A1

    公开(公告)日：2023-10-05

    申请号：US17710773

    申请日：2022-03-31

    Applicant: Texas Instruments Incorporated

    Inventor： Clint Alan Naquin ,  Henry Litzmann Edwards ,  Alexei Sadovnikov

    IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06

    CPC classification number: H01L29/7823 ,  H01L29/0653 ,  H01L29/66689

    Abstract: A microelectronic device including a substrate having a semiconductor material containing a laterally diffused metal oxide semiconductor (LDMOS) transistor, including a body region of a first conductivity type and a drift region of an opposite conductivity type. A gate dielectric layer over a channel region of the body, the gate dielectric extending over a junction between a body region and the drift region with a gate electrode on the gate dielectric and a drain contact in the drain drift region, having the second conductivity type. A field relief dielectric layer on the drain drift region extending from the drain region to the gate dielectric, having a thickness greater than the gate dielectric layer. A silicide-blocking layer extends from the drain region toward the gate, providing an unsilicided portion of the drift region at the substrate top surface between the drain region and the gate.

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