公开(公告)号：US09240446B2

公开(公告)日：2016-01-19

申请号：US14807276

申请日：2015-07-23

Applicant: Texas Instruments Incorporated

Inventor： Guru Mathur ,  Marie Denison ,  Sameer Pendharkar

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/06 ,  H01L29/66 ,  H01L21/762 ,  H01L29/10 ,  H01L21/266

CPC classification number: H01L29/063 ,  H01L21/266 ,  H01L21/76232 ,  H01L21/823418 ,  H01L21/823456 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7809 ,  H01L29/7811 ,  H01L29/7813

Abstract: A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define at least one vertical drift region bounded on at least two opposite sides by the deep trench structures. The deep trench structures include dielectric liners. The deep trench structures are spaced so as to form RESURF regions for the drift region. Vertical gates are formed in vertically oriented gate trenches in the dielectric liners of the deep trench structures, abutting the vertical drift regions. A body implant mask for implanting dopants for the transistor body is also used as an etch mask for forming the vertically oriented gate trenches in the dielectric liners.

公开(公告)号：US09093301B2

公开(公告)日：2015-07-28

申请号：US13789949

申请日：2013-03-08

Applicant: Texas Instruments Incorporated

Inventor： Sameer Pendharkar ,  Naveen Tipirneni

IPC: H03K17/687 ,  H01L27/088 ,  H01L21/8236 ,  H01L21/8234 ,  H01L21/8252 ,  H01L21/8258 ,  H01L27/06

CPC classification number: H03K17/6872 ,  H01L21/823418 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823475 ,  H01L21/8236 ,  H01L21/8252 ,  H01L21/8258 ,  H01L27/0605 ,  H01L27/0883 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/16 ,  H01L29/2003 ,  H01L29/66446 ,  H01L29/7833 ,  H02M5/2573 ,  H03F3/193 ,  H03F3/195 ,  H03K17/6871 ,  H03K17/6877 ,  H03K2017/6875

Abstract: A semiconductor device includes a depletion mode GaN FET and an integrated driver/cascode IC. The integrated driver/cascode IC includes an enhancement mode cascoded NMOS transistor which is connected in series to a source node of the GaN FET. The integrated driver/cascode IC further includes a driver circuit which conditions a gate input signal and provides a suitable digital waveform to a gate node of the cascoded NMOS transistor. The cascoded NMOS transistor and the driver circuit are formed on a same silicon substrate.

Abstract translation: 半导体器件包括耗尽型GaN FET和集成驱动器/共源共栅IC。 集成驱动器/共源共极集成电路包括与GaN FET的源极节点串联连接的增强型共模NMOS晶体管。 集成驱动器/共源共极IC还包括驱动电路，其调节栅极输入信号并向级联的NMOS晶体管的栅极节点提供合适的数字波形。 级联的NMOS晶体管和驱动电路形成在相同的硅衬底上。

公开(公告)号：US20150021614A1

公开(公告)日：2015-01-22

申请号：US13946415

申请日：2013-07-19

Applicant: Texas Instruments Incorporated

Inventor： Hassan P. Forghani-Zadeh ,  Sameer Pendharkar

IPC: H01L27/088 ,  H01L29/20

CPC classification number: H01L27/0883 ,  H01L21/8236 ,  H01L29/2003 ,  H01L29/7787 ,  H03K17/102 ,  H03K17/567 ,  H03K2017/6875

Abstract: A semiconductor device includes a depletion mode GaN FET cascoded with an enhancement mode NMOS transistor. A gate of the GaN FET is electrically coupled to a source of the NMOS transistor through a gate network. The gate network controls at least one of a turn-on time and a turn-off time of the GaN FET. The gate network may be controlled by an input signal to a gate of the NMOS transistor.

Abstract translation: 半导体器件包括与增强型NMOS晶体管级联的耗尽型GaN FET。 GaN FET的栅极通过栅极网络电耦合到NMOS晶体管的源极。 栅极网络控制GaN FET的导通时间和关断时间中的至少一个。 栅极网络可以由到NMOS晶体管的栅极的输入信号来控制。

公开(公告)号：US08933461B2

公开(公告)日：2015-01-13

申请号：US13886410

申请日：2013-05-03

Applicant: Texas Instruments Incorporated

Inventor： Sameer Pendharkar ,  Naveen Tipirneni

IPC: H01L31/0256 ,  H01L21/336 ,  H01L29/20 ,  H01L29/66 ,  H01L29/778 ,  H01L21/8252 ,  H01L21/8258 ,  H01L27/06 ,  H01L29/423 ,  H01L29/10

CPC classification number: H01L29/2003 ,  H01L21/8252 ,  H01L21/8258 ,  H01L27/0605 ,  H01L29/1066 ,  H01L29/42316 ,  H01L29/4236 ,  H01L29/66477 ,  H01L29/7786

Abstract: A semiconductor device includes an enhancement mode GaN FET with a depletion mode GaN FET electrically coupled in series between a gate node of the enhancement mode GaN FET and a gate terminal of the semiconductor device. A gate node of the depletion mode GaN FET is electrically coupled to a source node of the enhancement mode GaN FET. A source node of said enhancement mode GaN FET is electrically coupled to a source terminal of the semiconductor device, a drain node of the enhancement mode GaN FET is electrically coupled to a drain terminal of said semiconductor device, and a drain node of the depletion mode GaN FET is electrically coupled to a gate terminal of the semiconductor device.

Abstract translation: 半导体器件包括在增强型GaN FET的栅极节点和半导体器件的栅极端子之间串联电耦合的耗尽型GaN FET的增强型GaN FET。 耗尽型GaN FET的栅极节点电耦合到增强型GaNFET的源极节点。 所述增强型GaN FET的源节点电耦合到半导体器件的源极端子，增强型GaNFET的漏极节点电耦合到所述半导体器件的漏极端子，并且耗尽模式的漏极节点 GaN FET电耦合到半导体器件的栅极端子。

公开(公告)号：US08829613B1

公开(公告)日：2014-09-09

申请号：US13886709

申请日：2013-05-03

Applicant: Texas Instruments Incorporated

Inventor： Sameer Pendharkar ,  Naveen Tipirneni

IPC: H01L29/76

CPC classification number: H01L29/404 ,  H01L21/31144 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/66871 ,  H01L29/78 ,  H01L29/812

Abstract: A semiconductor device is formed with a stepped field plate over at least three sequential regions in which a total dielectric thickness under the stepped field plate is at least 10 percent thicker in each region compared to the preceding region. The total dielectric thickness in each region is uniform. The stepped field plate is formed over at least two dielectric layers, of which at least all but one dielectric layer is patterned so that at least a portion of a patterned dielectric layer is removed in one or more regions of the stepped field plate.

Abstract translation: 半导体器件在至少三个连续区域上形成有台阶式场板，其中在阶梯式场板下的总电介质厚度与先前区域相比在每个区域中至少为10％以上。 各区域的总电介质厚度均匀。 阶梯式场板形成在至少两个电介质层上，至少两个电介质层至少形成一个电介质层，使得图案化的电介质层的至少一部分在阶梯式场板的一个或多个区域中被去除。

公开(公告)号：US08766359B2

公开(公告)日：2014-07-01

申请号：US14073472

申请日：2013-11-06

Applicant: Texas Instruments Incorporated

Inventor： Marie Denison ,  Sameer Pendharkar

IPC: H01L29/78

CPC classification number: H01L29/7816 ,  H01L21/76224 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0882 ,  H01L29/4236 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

Abstract: An integrated circuit containing an extended drain MOS transistor with deep semiconductor (SC) RESURF trenches in the drift region, in which each deep SC RESURF trench has a semiconductor RESURF layer at a sidewall of the trench contacting the drift region. The semiconductor RESURF layer has an opposite conductivity type from the drift region. The deep SC RESURF trenches have depth:width ratios of at least 5:1, and do not extend through a bottom surface of the drift region. A process of forming an integrated circuit with deep SC RESURF trenches in the drift region by etching undersized trenches and counterdoping the sidewall region to form the semiconductor RESURF layer. A process of forming an integrated circuit with deep SC RESURF trenches in the drift region by etching trenches and growing an epitaxial layer on the sidewall region to form the semiconductor RESURF layer.

Abstract translation: 一种集成电路，其包含在漂移区域中具有深半导体（SC）RESURF沟槽的扩展漏极MOS晶体管，其中每个深的SC RESURF沟槽在与漂移区接触的沟槽的侧壁处具有半导体RESURF层。 半导体RESURF层具有与漂移区相反的导电类型。 深的SC RESURF沟槽具有至少5：1的深度：宽度比，并且不延伸穿过漂移区域的底部表面。 通过蚀刻尺寸不足的沟槽和反向掺杂侧壁区以形成半导体RESURF层，在漂移区中形成具有深SC RESURF沟槽的集成电路的工艺。 通过蚀刻沟槽并在侧壁区域上生长外延层以形成半导体RESURF层，在漂移区中形成具有深SC RESURF沟槽的集成电路的工艺。

公开(公告)号：US08759879B1

公开(公告)日：2014-06-24

申请号：US13886688

申请日：2013-05-03

Applicant: Texas Instruments Incorporated

Inventor： Naveen Tipirneni ,  Sameer Pendharkar ,  Jungwoo Joh

IPC: H01L31/109

CPC classification number: H01L29/2003 ,  H01L29/063 ,  H01L29/1075 ,  H01L29/1087 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/7786

Abstract: A semiconductor device containing a GaN FET has n-type doping in at least one III-N semiconductor layer of a low-defect layer and an electrical isolation layer below a barrier layer. A sheet charge carrier density of the n-type doping is 1 percent to 200 percent of a sheet charge carrier density of the two-dimensional electron gas.

Abstract translation: 包含GaN FET的半导体器件在低缺陷层的至少一个III-N半导体层和阻挡层下面的电隔离层中具有n型掺杂。 n型掺杂的片电荷载流子密度为二维电子气的片电荷载流子密度的1〜200％。

公开(公告)号：US20130105909A1

公开(公告)日：2013-05-02

申请号：US13663015

申请日：2012-10-29

Applicant: Texas Instruments Incorporated

Inventor： Binghua Hu ,  Pinghai Hao ,  Sameer Pendharkar ,  Seetharaman Sridhar ,  Jarvis Jacobs

IPC: H01L27/092 ,  H01L21/336 ,  H01L21/8238

CPC classification number: H01L27/092 ,  H01L21/761 ,  H01L21/823814 ,  H01L21/823878 ,  H01L27/0883 ,  H01L29/06 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/408 ,  H01L29/41758 ,  H01L29/42364 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7833 ,  H01L29/7835 ,  H01L29/7836

Abstract: An integrated circuit containing a first plurality of MOS transistors operating in a low voltage range, and a second plurality of MOS transistors operating in a mid voltage range, may also include a high-voltage MOS transistor which operates in a third voltage range significantly higher than the low and mid voltage ranges, for example 20 to 30 volts. The high-voltage MOS transistor has a closed loop configuration, in which a drain region is surrounded by a gate, which is in turn surrounded by a source region, so that the gate does not overlap field oxide. The integrated circuit may include an n-channel version of the high-voltage MOS transistor and/or a p-channel version of the high-voltage MOS transistor. Implanted regions of the n-channel version and the p-channel version are formed concurrently with implanted regions in the first and second pluralities of MOS transistors.

公开(公告)号：US20230395589A1

公开(公告)日：2023-12-07

申请号：US18451292

申请日：2023-08-17

Applicant: Texas Instruments Incorporated

Inventor： Sunglyong Kim ,  David LaFonteese ,  Seetharaman Sridhar ,  Sameer Pendharkar

IPC: H01L27/02 ,  H01L29/10 ,  H01L29/78 ,  H01L29/08

CPC classification number: H01L27/0259 ,  H01L29/1095 ,  H01L29/7818 ,  H01L29/0878 ,  H01L29/7816 ,  H01L29/0882 ,  H01L29/0619

Abstract: An electrostatic discharge (ESD) protection structure that provides snapback protections to one or more high voltage circuit components. The ESD protection structure can be integrated along a peripheral region of a high voltage circuit, such as a high side gate driver of a driver circuit. The ESD protection structure includes a bipolar transistor structure interfacing with a PN junction of a high voltage device, which is configured to discharge the ESD current during an ESD event. The bipolar transistor structure has a collector region overlapping the PN junction, a base region embedded with sufficient pinch resistance to launch the snapback protection, and an emitter region for discharging the ESD current.

公开(公告)号：US20210408306A1

公开(公告)日：2021-12-30

申请号：US17474492

申请日：2021-09-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： He Lin ,  Sameer Pendharkar

IPC: H01L31/0352 ,  H01L31/0224 ,  H01L31/0216 ,  H01L31/02 ,  H01L27/144 ,  H01L31/103 ,  H01L31/0304 ,  H01L25/04 ,  H01L31/18

Abstract: A photo detector includes a superlattice with an undoped first semiconductor layer including undoped intrinsic semiconductor material, a doped second semiconductor layer having a first conductivity type on the first semiconductor layer, an undoped third semiconductor layer including undoped intrinsic semiconductor material on the second semiconductor layer, and a fourth semiconductor layer having a second opposite conductivity type on the third semiconductor layer, along with a first contact having the first conductivity type in the first, second, third, and fourth semiconductor layers, and a second contact having the second conductivity type and spaced apart from the first contact in the first, second, third, and fourth semiconductor layers. An optical shield on a second shielded portion of a top surface of the fourth semiconductor layer establishes electron and hole lakes. A packaging structure includes an opening that allows light to enter an exposed first portion of the top surface of the fourth semiconductor layer.