公开(公告)号：US20240047316A1

公开(公告)日：2024-02-08

申请号：US17880057

申请日：2022-08-03

Applicant: Texas Instruments Incorporated

Inventor： Yiqi Tang ,  Rajen Murugan ,  Chittranjan Gupta

IPC: H01L23/495 ,  H05K1/18 ,  H05K1/11 ,  H01L23/00

CPC classification number: H01L23/49555 ,  H05K1/181 ,  H05K1/115 ,  H01L24/48 ,  H01L24/49 ,  H05K2201/10363 ,  H01L23/3107

Abstract: An electronic device includes conductive leads, a conductive crossbar, and first and second bond wires. The conductive leads are arranged in a row along a side of a package structure and include a conductive first lead, a conductive second lead, and a conductive third lead. The first and second leads are non-adjacent, the third lead is between the first and second leads in the row, and the crossbar electrically connects the first and second leads. The first bond wire electrically connects a first conductive feature of a semiconductor die to one of the crossbar, the first lead, and the second lead, and the second bond wire electrically connects a second conductive feature of the semiconductor die to the third lead.

公开(公告)号：US20230352387A1

公开(公告)日：2023-11-02

申请号：US17733414

申请日：2022-04-29

Applicant: Texas Instruments Incorporated

Inventor： Li Jiang ,  Yiqi Tang ,  Usman Mahmood Chaudhry ,  Thiha Shwe

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/66

CPC classification number: H01L23/49827 ,  H01L23/49816 ,  H01L24/17 ,  H01L22/34 ,  H01L2224/1413 ,  H01L2224/1403

Abstract: An example semiconductor package comprises an integrated circuit die having a first surface with a first array of electrode pads. A laminate substrate has an upper surface with a second array of electrode pads. The electrode pads of the first array are connected to corresponding electrode pads of the second array using a solder bump. The laminate substrate has a lower surface with a third array of electrode pads. The electrodes of the third array are coupled to corresponding electrodes of the second array by a laminate wiring structure within the laminate substrate. A first electrode on the lower surface is coupled to a second electrode on the lower surface by a chain of vias through the laminate substrate. The chain of vias is not connected to the integrated circuit die.

公开(公告)号：US20230317644A1

公开(公告)日：2023-10-05

申请号：US17710931

申请日：2022-03-31

Applicant: Texas Instruments Incorporated

Inventor： Juan Alejandro Herbsommer ,  Yiqi Tang ,  Rajen Manicon Murugan

IPC: H01L23/66 ,  H01L23/00 ,  H01L23/495 ,  H01Q1/38 ,  H01Q1/22 ,  H01Q3/36 ,  H01Q21/06 ,  H01Q3/44 ,  H01Q5/371 ,  H01Q1/42 ,  H01Q15/00

CPC classification number: H01L23/66 ,  H01L24/16 ,  H01L24/13 ,  H01L23/49534 ,  H01L23/49548 ,  H01L23/49541 ,  H01Q1/38 ,  H01Q1/2283 ,  H01Q3/36 ,  H01Q21/065 ,  H01Q3/44 ,  H01Q5/371 ,  H01Q1/422 ,  H01Q15/0026 ,  H01L2223/6616 ,  H01L2223/6677 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/73204 ,  H01L2224/32245 ,  H01L2224/16245 ,  H01L2224/13147 ,  H01L2224/13611 ,  H01L2224/13639 ,  H01L2224/13647 ,  H01L2924/182 ,  H01Q21/10

Abstract: Described examples include an apparatus having a first antenna and a second antenna formed in a first layer on a first surface of a multilayer package substrate, the multilayer package substrate having layers including patterned conductive portions and dielectric portions, the multilayer package substrate having a second surface opposite the first surface. The apparatus also has an isolation wall formed in the multilayer package substrate formed in at least a second and a third layer in the multilayer package substrate and a semiconductor die mounted to the first surface of the multilayer package substrate spaced from and coupled to the first antenna and the second antenna.

公开(公告)号：US20230317581A1

公开(公告)日：2023-10-05

申请号：US17710912

申请日：2022-03-31

Applicant: Texas Instruments Incorporated

Inventor： Yiqi Tang ,  Jie Chen ,  Chittranjan Mojan Gupta ,  Rajen Muricon Murugan

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/81 ,  H01L2924/15311 ,  H01L2224/16227 ,  H01L24/32 ,  H01L2224/32225 ,  H01L24/73 ,  H01L2224/73204

Abstract: In a described example, an apparatus includes: a multilayer package substrate including a die mount area on a die side surface and comprising power pads and ground pads on an opposing board side surface, the multilayer package substrate including post connect locations on the die side surface for receiving power post connects and for receiving ground post connects for a flip chip mounted semiconductor device, the power post connect locations and the ground post connect locations positioned in the die mount area, the power post connect locations and the ground post connect locations intermixed in the die mount area; and a semiconductor device having post connects extending from bond pads on a device side surface of the semiconductor device mounted to the die side surface of the multilayer package substrate by solder joints between the post connects and the post connect locations.

公开(公告)号：US20230268259A1

公开(公告)日：2023-08-24

申请号：US17677042

申请日：2022-02-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yiqi Tang ,  Guangxu Li ,  Rajen Manicon Murugan

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/49822 ,  H01L23/3107 ,  H01L24/16 ,  H01L21/4857 ,  H01L21/56 ,  H01L24/81 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/16227 ,  H01L2224/81007 ,  H01L2224/32227 ,  H01L2224/8385

Abstract: An electronic device with a multilevel package substrate having multiple levels including a first level having conductive leads and a final level having conductive landing areas along a side, as well as a die mounted to the multilevel package substrate and having conductive terminals electrically coupled to respective ones of the conductive leads, and a package structure that encloses the die and a portion of the multilevel package substrate, where the multilevel package substrate has a conductive elevated trace layer with a confinement feature that extends outward from the side of the final level along a third direction that is orthogonal to the first and second directions, the confinement feature having a sidewall configured to laterally confine one of a solder, an adhesive, a side of a passive component, and a side of the die.

公开(公告)号：US11600555B2

公开(公告)日：2023-03-07

申请号：US17233205

申请日：2021-04-16

Applicant: Texas Instruments Incorporated

Inventor： Rajen Manicon Murugan ,  Yiqi Tang

IPC: H01L23/495 ,  H01L21/56 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor package includes a multilayer package substrate with a top layer including top filled vias through a top dielectric layer and top metal layer providing a top surface for leads and traces connected to the leads, and a bottom layer including bottom filled vias including contact pads through a bottom dielectric and metal layer. The top filled vias are for connecting the bottom and top metal layer. The bottom metal filled vias are for connecting the bottom metal layer to the contact pads. An integrated circuit (IC) die has nodes in its circuitry connected to the bond pads. The IC die is flipchip mounted onto the leads. A passive device(s) is surface mounted by an electrically conductive material on the top metal layer electrically connected between at least one adjacent pair of the leads. A mold compound is for encapsulating at least the IC die and passive device.

公开(公告)号：US20230021179A1

公开(公告)日：2023-01-19

申请号：US17379549

申请日：2021-07-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yiqi Tang ,  Rajen Manicon Murugan ,  Chittranjan Mohan Gupta ,  Jie Chen

IPC: H01L49/02 ,  H01F17/00 ,  H05K3/46 ,  H05K1/11 ,  H02M3/158

Abstract: A semiconductor device includes a die having an input port and an output port. The semiconductor device also includes a multilayer package substrate with pads on a surface of the multilayer package substrate configured to be coupled to circuit components of a printed circuit board. The multilayer package substrate also includes a passive filter comprising an input port and an output port, and a planar inductor. The planar inductor is coupled to a given pad of the pads of the multilayer package substrate with a first via of the multilayer package substrate and to the input port of the die with a second via of the multilayer package substrate. The planar inductor extends parallel to the surface of the multilayer package substrate.

公开(公告)号：US11557722B2

公开(公告)日：2023-01-17

申请号：US17142539

申请日：2021-01-06

Applicant: Texas Instruments Incorporated

Inventor： Ming Li ,  Yiqi Tang ,  Jie Chen ,  Enis Tuncer ,  Usman Mahmood Chaudhry ,  Tony Ray Larson ,  Rajen Manicon Murugan ,  John Paul Tellkamp ,  Satyendra Singh Chauhan

IPC: H01L43/14 ,  G01R33/07 ,  G01R15/20 ,  H01L43/06 ,  H01L23/495 ,  G01R33/00

Abstract: A Hall-effect sensor package includes and an IC die including a Hall-Effect element and a leadframe including leads on a first side providing a first field generating current (FGC) path including≥1 first FGC input pin coupled by a reduced width first curved head over or under the Hall-effect sensor element to ≥1 first FGC output pin, and second leads on a second side of the package. Some leads on the second side are attached to bond pads on the IC die including the output of the Hall-effect element. A clip is attached at one end to the first FGC input pin and at another end to a location on the first FGC output pin, having a reduced width second curved head in between that is over or under the Hall-effect sensor element opposite the first head.

公开(公告)号：US11545420B2

公开(公告)日：2023-01-03

申请号：US16787327

申请日：2020-02-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yiqi Tang ,  Liang Wan ,  William Todd Harrison ,  Manu Joseph Prakuzhy ,  Rajen Manicon Murugan

IPC: H01L23/495 ,  H02M3/158 ,  H01L23/00

Abstract: In some examples, a direct current (DC)-DC power converter package comprises a controller, a conductive member, and a first field effect transistor (FET) coupled to the controller and having a first source and a first drain, the first FET coupled to a first portion of the conductive member. The package also comprises a second FET coupled to the controller and having a second source and a second drain, the second FET coupled to a second portion of the conductive member, the first and second portions of the conductive member being non-overlapping in a horizontal plane. The first and second FETs are non-overlapping.

公开(公告)号：US20220285293A1

公开(公告)日：2022-09-08

申请号：US17752037

申请日：2022-05-24

Applicant: Texas Instruments Incorporated

Inventor： Vivek Swaminathan Sridharan ,  Yiqi Tang ,  Christopher Daniel Manack ,  Rajen Manicon Murugan ,  Liang Wan ,  Hiep Xuan Nguyen

IPC: H01L23/60 ,  H01L23/495 ,  H01L23/00 ,  H01L33/00 ,  H01L33/62

Abstract: A system in a package (SIP) includes carrier layer regions that have a dielectric material with a metal post therethrough, where adjacent carrier layer regions define a gap. A driver IC die is positioned in the gap having nodes connected to bond pads exposed by openings in a top side of a first passivation layer, with the bond pads facing up. A dielectric layer is on the first passivation layer and carrier layer region that includes filled through vias coupled to the bond pads and to the metal post. A light blocking layer is on sidewalls and a bottom of the substrate. A first device includes a light emitter that has first bondable features. The light blocking layer can block at least 90% of incident light. The first bondable features are flipchip mounted to a first portion of the bond pads.