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公开(公告)号：US20060138503A1
公开(公告)日：2006-06-29
申请号：US11084150
申请日：2005-03-21
IPC分类号： H01L29/94
CPC分类号： H01L27/11502 , H01L27/0207 , H01L27/11507
摘要： A ferroelectric memory comprises a first transistor connected between N1 and N2 nodes, a second transistor connected between the N2 node and an N3 node, a first transistor connected between P1 and P2 nodes, a second transistor connected between the P2 node and a P3 node, a first wiring formed in a first wiring layer to interconnect the N1 node and the P1 node, a second wiring formed in the first wiring layer to interconnect the N3 node and the P3 node, a third wiring formed in a second wiring layer different from the first wiring layer to interconnect the N2 node and the P2 node, a first capacitor whose first electrode is connected to the first wiring, and a second capacitor whose first electrode is connected to the second wiring. Second electrodes of the first and second capacitors are both connected to the N2 node or the P2 node.
摘要翻译： 铁电存储器包括连接在N 1和N 2个节点之间的第一晶体管，连接在N 2节点和N 3节点之间的第二晶体管，连接在P 1和P 2节点之间的第一晶体管，连接在P 2节点和P 3节点，形成在第一布线层中以互连N 1节点和P 1节点的第一布线;形成在第一布线层中以互连N 3节点和P 3节点的第二布线， 形成在与所述第一布线层不同以将所述N 2节点和所述P 2节点互连的第二布线层的第三布线，其第一电极连接到所述第一布线的第一电容器，以及第一电极，其第一电极连接到 第二线。 第一和第二电容器的第二电极都连接到N 2节点或P 2节点。
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公开(公告)号：US20060092748A1
公开(公告)日：2006-05-04
申请号：US11258922
申请日：2005-10-27
IPC分类号： G11C8/00
CPC分类号： G11C11/22
摘要： A semiconductor memory according to an example of the present invention comprises first and second bit lines having a twisted bit-line architecture in which the first and second bit lines are alternately twisted at a constant period in first and second columns, a first cell block which is disposed in the first column, a first block select transistor which is connected between the first or second bit line and one end of the first cell block, a second cell block which is disposed in the second column, and a second block select transistor which is connected between the second or first bit line and one end of the second cell block.
摘要翻译： 根据本发明的示例的半导体存储器包括具有扭曲位线架构的第一和第二位线，其中第一和第二位线在第一和第二列中以恒定周期交替地扭曲;第一单元块，其 设置在第一列中，第一块选择晶体管连接在第一或第二位线与第一单元块的一端之间，第二单元块设置在第二列中，第二块选择晶体管， 连接在第二或第二位线与第二单元块的一端之间。
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公开(公告)号：US5981971A
公开(公告)日：1999-11-09
申请号：US41727
申请日：1998-03-13
申请人： Tadashi Miyakawa
发明人： Tadashi Miyakawa
IPC分类号： G01R31/28 , G01R31/317 , G01R31/3185 , H01L21/02 , H01L21/66 , H01L23/58 , G01R31/26
CPC分类号： H01L22/32 , G01R31/31719 , G01R31/318505 , G01R31/318511 , H01L2224/05554 , H01L2924/13091 , Y10S257/922
摘要： In a semiconductor wafer (1), an internal circuit such as a ROM formed at a product region or a chip (2) can be tested via a test pad (5) formed on a scribe line (3). Here, since the test pad (5) is formed on the scribe line (3), after the semiconductor wafer has been once cut off and separated away from each other as chips along the scribe lines (3), respectively, since the test pads (5) are all broken off, ROM test will not be executed again. In other words, since the test conditions of the product test of the separated chip (2) cannot be decoded or deciphered by another person, it is possible to provide a semiconductor device of high secrecy, which can be preferably used as an IC card.
摘要翻译： 在半导体晶片（1）中，可以通过形成在划线（3）上的测试焊盘（5）来测试形成在产品区域或芯片（2）上的诸如ROM的内部电路。 这里，由于在刻划线（3）上形成了测试焊盘（5），所以在半导体晶片被一次切断并分离成分别作为沿划线（3）的芯片之后，由于测试焊盘 （5）全部断开，ROM测试将不再执行。 换句话说，由于分离芯片（2）的产品测试的测试条件不能被另一个人解码或解密，所以可以提供可以优选用作IC卡的高度保密性的半导体器件。
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公开(公告)号：US5917750A
公开(公告)日：1999-06-29
申请号：US955288
申请日：1997-10-21
申请人： Tadashi Miyakawa , Nobuaki Ohtsuka
发明人： Tadashi Miyakawa , Nobuaki Ohtsuka
IPC分类号： G01R31/28 , G06F12/14 , G06F21/02 , G11C16/02 , G11C16/22 , G11C29/12 , G11C29/52 , G11C11/34
摘要： A plurality of erase circuits are provided for the blocks BLK(0) to BLK(n), each for one block. Protect circuits are connected to the erase circuits, respectively. The protects circuits generate protect signals PROT0 to PROTn, respectively. Each protect signal indicates whether the protect circuit is set in protect mode or not. Each erase circuit receives the protect signal from the protect circuit connected to it. A unit provided in the erase circuit determines, from the protect signal, whether the protect circuit is set in the protect mode. The unit changes the voltage applied to the sources of the memory cells of the cell block connected to the erase circuit, in accordance with whether the protect circuit is set in the protect mode or not. When a voltage is applied to the sources of the memory cells, a data item of a logic value is read from each memory cell. When a different voltage is applied to the sources of the memory cells, a data item of the other logic value is read from each memory cell. Hence, whether or not the protect circuits are set in protect mode can be determined, without erasing or writing data in the block of the memory cell array.
摘要翻译： 为块BLK（0）至BLK（n）提供多个擦除电路，每个块用于一个块。 保护电路分别连接到擦除电路。 保护电路分别产生保护信号PROT0至PROTn。 每个保护信号指示保护电路是否设置为保护模式。 每个擦除电路从与其连接的保护电路接收保护信号。 设置在擦除电路中的单元根据保护信号确定保护电路是否设置在保护模式。 根据保护电路是否设置在保护模式，该单元改变施加到连接到擦除电路的单元块的存储单元的源极的电压。 当向存储器单元的源施加电压时，从每个存储器单元读取逻辑值的数据项。 当将不同的电压施加到存储器单元的源时，从每个存储器单元读取另一个逻辑值的数据项。 因此，可以确定保护电路是否设置为保护模式，而不会在存储单元阵列的块中擦除或写入数据。
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55.发明授权Nonvolatile semiconductor memory having a stress relaxing voltage applied to erase gate during data write 失效在数据写入期间具有施加到擦除栅极的应力松弛电压的非易失性半导体存储器
公开(公告)号：US5787034A
公开(公告)日：1998-07-28
申请号：US813951
申请日：1997-03-03
申请人： Sachiko Omino , Tadashi Miyakawa , Masamichi Asano
发明人： Sachiko Omino , Tadashi Miyakawa , Masamichi Asano
IPC分类号： G11C17/00 , G11C16/02 , G11C16/04 , G11C16/06 , G11C16/16 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/0416 , G11C16/16
摘要： A non-volatile semiconductor memory having: a memory cell array having non-volatile memory cells disposed in a matrix form, each memory cell having a floating gate, a control gate, an erase gate, a source and a drain, and data being written through injection of electrons into the floating gate and erased through removal of electrons from the floating gate; and a peripheral circuit driven by a high voltage power source and a low voltage power source, predetermined voltages being applied to the control gate, erase gate and drain respectively of each memory cell to enter one of a data write mode, data erase mode and data read mode, in the data write mode, high voltages being applied to the control gate and drain of the memory cell to be data-written, a stress relaxing voltage being applied to each erase gate of memory cells not to be data-written, and the stress relaxing voltage being an intermediate voltage between the voltages of the high and low power sources.
摘要翻译： 一种非易失性半导体存储器，具有：具有以矩阵形式设置的非易失性存储单元的存储单元阵列，每个存储单元具有浮置栅极，控制栅极，擦除栅极，源极和漏极以及被写入的数据 通过将电子注入浮栅并通过从浮栅去除电子而被擦除; 以及由高电压电源和低电压电源驱动的外围电路，分别向控制栅极施加预定电压，分别对每个存储单元擦除栅极和漏极以进入数据写入模式，数据擦除模式和数据之一 读取模式，在数据写入模式下，高电压被施加到要被数据写入的存储单元的控制栅极和漏极，应力松弛电压被施加到不被数据写入的存储器单元的每个擦除栅极，以及 应力松弛电压是高电源和低电源电压之间的中间电压。
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56.发明授权Nonvolatile semiconductor memory having a stress relaxing voltage applied to erase gate during data write 失效在数据写入期间具有施加到擦除栅极的应力松弛电压的非易失性半导体存储器
公开(公告)号：US5636160A
公开(公告)日：1997-06-03
申请号：US570575
申请日：1995-12-11
申请人： Sachiko Omino , Tadashi Miyakawa , Masamichi Asano
发明人： Sachiko Omino , Tadashi Miyakawa , Masamichi Asano
IPC分类号： G11C17/00 , G11C16/02 , G11C16/04 , G11C16/06 , G11C16/16 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/0416 , G11C16/16
摘要： A non-volatile semiconductor memory having: a memory cell array having non-volatile memory cells disposed in a matrix form, each memory cell having a floating gate, a control gate, an erase gate, a source and a drain, and data being written through injection of electrons into the floating gate and erased through removal of electrons from the floating gate; and a peripheral circuit driven by a high voltage power source and a low voltage power source, predetermined voltages being applied to the control gate, erase gate and drain respectively of each memory cell to enter one of a data write mode, data erase mode and data read mode, in the data write mode, high voltages being applied to the control gate and drain of the memory cell to be data-written, a stress relaxing voltage being applied to each erase gate of memory cells not to be data-written, and the stress relaxing voltage being an intermediate voltage between the voltages of the high and low power sources.
摘要翻译： 一种非易失性半导体存储器，具有：具有以矩阵形式设置的非易失性存储单元的存储单元阵列，每个存储单元具有浮置栅极，控制栅极，擦除栅极，源极和漏极以及被写入的数据 通过将电子注入浮栅并通过从浮栅去除电子而被擦除; 以及由高电压电源和低电压电源驱动的外围电路，分别向控制栅极施加预定电压，分别对每个存储单元擦除栅极和漏极以进入数据写入模式，数据擦除模式和数据之一 读取模式，在数据写入模式下，高电压被施加到要被数据写入的存储单元的控制栅极和漏极，应力松弛电压被施加到不被数据写入的存储器单元的每个擦除栅极，以及 应力松弛电压是高电源和低电源电压之间的中间电压。
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公开(公告)号：US5566113A
公开(公告)日：1996-10-15
申请号：US412864
申请日：1995-03-29
申请人： Hidetoshi Saito , Tadashi Miyakawa
发明人： Hidetoshi Saito , Tadashi Miyakawa
CPC分类号： G11C16/3445 , G11C16/10 , G11C16/16 , G11C16/3436 , G11C16/3459
摘要： A comparator compares data read out by a sensing amplifier with input data, and outputs equality data when both of the data are equal to each other, while the comparator outputs inequality data when both of the data are not equal to each other. When the comparator outputs inequality data for at least one time within a predetermined period decided by a control signal, the latch circuit latches and keeps outputting the inequality data. The latch circuit latches and outputs equality data when the comparator continuously outputs equality data within the period. Within the period decided by the control signal, the determination circuit determines whether or not writing has been completed on the basis of output data of the latch circuit. The re-write signal generator circuit sends a re-write signal to a write circuit when the determination circuit determines that writing is not yet completed.
摘要翻译： 比较器将由感测放大器读出的数据与输入数据进行比较，并且当两个数据彼此相等时输出相等数据，而当两个数据彼此不相等时，比较器输出不等式数据。 当比较器在由控制信号决定的预定时段内输出不等式数据至少一次时，锁存电路锁存并不断输出不等式数据。 当比较器在该周期内连续输出相等数据时，锁存电路锁存并输出相等的数据。 在由控制信号决定的时段内，确定电路基于锁存电路的输出数据确定是否已经完成写入。 当确定电路确定写入尚未完成时，重写信号发生器电路向写入电路发送重写信号。
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58.发明授权
公开(公告)号：US5426240A
公开(公告)日：1995-06-20
申请号：US271779
申请日：1994-07-07
IPC分类号： C07C29/09 , C07C31/42 , C07C45/63 , C07C45/81 , C07C45/82 , C07C47/14 , C07C47/16 , C07C45/00
摘要： A process for producing dichloroacetaldehyde hydrate together with chloral from acetaldehyde or para-aldehyde. The process comprises a step of chlorinating acetaldehyde or para-aldehyde to obtain a chlorinated solution containing dichloroacetaldehyde as a major component, a step of distilling this chlorinated solution to obtain a distillate having a boiling point of 90.degree.-100.degree. C. and containing 50% or more of dichloroacetaldehyde, a step of adding water to this distillate, crystallizing dichloroacetaldehyde hydrate, and separating the crystals, and a step of chlorinating the remaining aldehyde components into chloral. The process enables dichloroacetaldehyde hydrate to be separated at a high purity and the raw materials to be utilized efficiently.
摘要翻译： 一种从乙醛或对醛生产二氯乙醛水合物和氯醛的方法。 该方法包括将乙醛或对醛进行氯化以获得含有二氯乙醛为主要成分的氯化溶液的步骤，蒸馏该氯化溶液以获得沸点为90-100℃的馏出物并含有50 ％以上的二氯乙醛，向该馏出物中加入水，结晶二氯乙醛水合物和分离晶体的步骤，以及将剩余的醛组分氯化为氯醛的步骤。 该方法能够使二氯乙醛水合物以高纯度分离，并且有效地利用原料。
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59.发明授权
公开(公告)号：US5414139A
公开(公告)日：1995-05-09
申请号：US214123
申请日：1994-03-15
IPC分类号： B01J23/06 , B01J23/14 , C07B61/00 , C07C45/55 , C07C45/63 , C07D323/06 , C07C45/53 , C07C45/61
CPC分类号： C07D323/06 , C07C45/55 , C07C45/63
摘要： A process for manufacturing monochloroacetaldehyde trimer and chloral together by effectively utilizing a raw material acetaldehyde or para-aldehyde. The process comprises a step of chlorinating acetaldehyde or para-aldehyde to produce a chlorinated liquid of which the major component is monochloroacetaldehyde, a step comprising adding chloral to said chlorinated liquid and distilling the mixture to obtain a fraction of which the major components are monochloroacetaldehyde and chloral, a step of trimerizing monochloroacetaldehyde by reacting said fraction in the presence of a trimerization catalyst and separating the MCA trimer by filtration, and a step of chlorinating other fractions from said distillation step and the filtrate from said trimerization step to produce chloral. According to this process all raw material aldehydes and components derived from aldehydes which have not been consumed for the production of MCA trimer can be easily converted into chloral which is useful as an industrial chemical. The process is also free from the problem of the waste water treatment.
摘要翻译： 通过有效利用原料乙醛或对醛制备单氯乙醛三聚物和氯醛的方法。 该方法包括氯化乙醛或对醛以产生其主要成分为一氯乙醛的氯化液体的步骤，该步骤包括向所述氯化液体中加入氯醛并蒸馏该混合物，得到主要成分为一氯乙醛的馏分， 氯醛，通过在三聚催化剂存在下使所述级分反应并通过过滤分离MCA三聚体，以及从所述蒸馏步骤氯化其它级分的步骤和来自所述三聚步骤的滤液以产生氯醛的步骤，使一氯乙醛三聚。 根据该方法，所有原料醛和源自未用于生产MCA三聚体的醛的组分可以容易地转化成可用作工业化学品的氯醛。 该过程也没有废水处理的问题。
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公开(公告)号：US5153684A
公开(公告)日：1992-10-06
申请号：US734109
申请日：1991-07-24
IPC分类号： G11C16/04 , H01L27/115
CPC分类号： G11C16/0425 , H01L27/115
摘要： Source and drain regions of a second conductivity type are formed in a stripe form in the surface area of a semiconductor substrate of a first conductivity type. A first insulation film is formed on the source and drain regions of the substrate. A second thin insulation film having a tunnel effect is formed on that part of the substrate which lies between the source and drain regions. A floating gate is formed on the second insulation film. A third insulation film is formed on the first insulation film, the floating gate and that part of the substrate which lies between the source and drain regions and on which the second insulation film is not formed. A control gate is formed on the third insulation film in a stripe form extending in a direction which intersects the source and drain regions. An impurity region of the first conductivity type having an impurity concentration higher than the substrate is formed in the substrate except the source and drain regions and the portions lying below the control gate. A floating gate transistor is constituted to include the substrate, source and drain regions, second insulation film, floating gate, third insulation film and control gate. An offset transistor is constituted to include the substrate, source and drain regions, third insulation film and control gate. The first insulation film and the impurity region are used as an element isolation region of a memory cell.
摘要翻译： 在第一导电类型的半导体衬底的表面区域中形成第二导电类型的源区和漏区。 在基板的源极和漏极区域上形成第一绝缘膜。 在位于源区和漏区之间的衬底的该部分上形成具有隧道效应的第二薄绝缘膜。 在第二绝缘膜上形成浮栅。 在第一绝缘膜，浮栅和位于源极和漏极区之间的基板的那部分上形成第三绝缘膜，并且在其上不形成第二绝缘膜。 在第三绝缘膜上以与源极和漏极区相交的方向延伸的条形形成控制栅极。 在除了源极和漏极区域以及位于控制栅极下方的部分之外，在衬底中形成具有比衬底高的杂质浓度的第一导电类型的杂质区域。 浮栅晶体管构成为包括基板，源极和漏极区，第二绝缘膜，浮栅，第三绝缘膜和控制栅。 偏移晶体管构成为包括基板，源极和漏极区域，第三绝缘膜和控制栅极。 第一绝缘膜和杂质区用作存储单元的元件隔离区。
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