公开(公告)号：US5787034A

公开(公告)日：1998-07-28

申请号：US813951

申请日：1997-03-03

申请人： Sachiko Omino ,  Tadashi Miyakawa ,  Masamichi Asano

发明人： Sachiko Omino ,  Tadashi Miyakawa ,  Masamichi Asano

IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/04 ,  G11C16/06 ,  G11C16/16 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/0416 ,  G11C16/16

摘要： A non-volatile semiconductor memory having: a memory cell array having non-volatile memory cells disposed in a matrix form, each memory cell having a floating gate, a control gate, an erase gate, a source and a drain, and data being written through injection of electrons into the floating gate and erased through removal of electrons from the floating gate; and a peripheral circuit driven by a high voltage power source and a low voltage power source, predetermined voltages being applied to the control gate, erase gate and drain respectively of each memory cell to enter one of a data write mode, data erase mode and data read mode, in the data write mode, high voltages being applied to the control gate and drain of the memory cell to be data-written, a stress relaxing voltage being applied to each erase gate of memory cells not to be data-written, and the stress relaxing voltage being an intermediate voltage between the voltages of the high and low power sources.

摘要翻译： 一种非易失性半导体存储器，具有：具有以矩阵形式设置的非易失性存储单元的存储单元阵列，每个存储单元具有浮置栅极，控制栅极，擦除栅极，源极和漏极以及被写入的数据 通过将电子注入浮栅并通过从浮栅去除电子而被擦除; 以及由高电压电源和低电压电源驱动的外围电路，分别向控制栅极施加预定电压，分别对每个存储单元擦除栅极和漏极以进入数据写入模式，数据擦除模式和数据之一 读取模式，在数据写入模式下，高电压被施加到要被数据写入的存储单元的控制栅极和漏极，应力松弛电压被施加到不被数据写入的存储器单元的每个擦除栅极，以及 应力松弛电压是高电源和低电源电压之间的中间电压。

公开(公告)号：US5636160A

公开(公告)日：1997-06-03

申请号：US570575

申请日：1995-12-11

申请人： Sachiko Omino ,  Tadashi Miyakawa ,  Masamichi Asano

发明人： Sachiko Omino ,  Tadashi Miyakawa ,  Masamichi Asano

IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/04 ,  G11C16/06 ,  G11C16/16 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/0416 ,  G11C16/16

摘要： A non-volatile semiconductor memory having: a memory cell array having non-volatile memory cells disposed in a matrix form, each memory cell having a floating gate, a control gate, an erase gate, a source and a drain, and data being written through injection of electrons into the floating gate and erased through removal of electrons from the floating gate; and a peripheral circuit driven by a high voltage power source and a low voltage power source, predetermined voltages being applied to the control gate, erase gate and drain respectively of each memory cell to enter one of a data write mode, data erase mode and data read mode, in the data write mode, high voltages being applied to the control gate and drain of the memory cell to be data-written, a stress relaxing voltage being applied to each erase gate of memory cells not to be data-written, and the stress relaxing voltage being an intermediate voltage between the voltages of the high and low power sources.

摘要翻译： 一种非易失性半导体存储器，具有：具有以矩阵形式设置的非易失性存储单元的存储单元阵列，每个存储单元具有浮置栅极，控制栅极，擦除栅极，源极和漏极以及被写入的数据 通过将电子注入浮栅并通过从浮栅去除电子而被擦除; 以及由高电压电源和低电压电源驱动的外围电路，分别向控制栅极施加预定电压，分别对每个存储单元擦除栅极和漏极以进入数据写入模式，数据擦除模式和数据之一 读取模式，在数据写入模式下，高电压被施加到要被数据写入的存储单元的控制栅极和漏极，应力松弛电压被施加到不被数据写入的存储器单元的每个擦除栅极，以及 应力松弛电压是高电源和低电源电压之间的中间电压。

公开(公告)号：US5153684A

公开(公告)日：1992-10-06

申请号：US734109

申请日：1991-07-24

申请人： Atsushi Shoji ,  Masamichi Asano ,  Tadashi Miyakawa ,  Tadayuki Taura ,  Michiharu Inami

发明人： Atsushi Shoji ,  Masamichi Asano ,  Tadashi Miyakawa ,  Tadayuki Taura ,  Michiharu Inami

IPC分类号： G11C16/04 ,  H01L27/115

CPC分类号： G11C16/0425 ,  H01L27/115

摘要： Source and drain regions of a second conductivity type are formed in a stripe form in the surface area of a semiconductor substrate of a first conductivity type. A first insulation film is formed on the source and drain regions of the substrate. A second thin insulation film having a tunnel effect is formed on that part of the substrate which lies between the source and drain regions. A floating gate is formed on the second insulation film. A third insulation film is formed on the first insulation film, the floating gate and that part of the substrate which lies between the source and drain regions and on which the second insulation film is not formed. A control gate is formed on the third insulation film in a stripe form extending in a direction which intersects the source and drain regions. An impurity region of the first conductivity type having an impurity concentration higher than the substrate is formed in the substrate except the source and drain regions and the portions lying below the control gate. A floating gate transistor is constituted to include the substrate, source and drain regions, second insulation film, floating gate, third insulation film and control gate. An offset transistor is constituted to include the substrate, source and drain regions, third insulation film and control gate. The first insulation film and the impurity region are used as an element isolation region of a memory cell.

摘要翻译： 在第一导电类型的半导体衬底的表面区域中形成第二导电类型的源区和漏区。 在基板的源极和漏极区域上形成第一绝缘膜。 在位于源区和漏区之间的衬底的该部分上形成具有隧道效应的第二薄绝缘膜。 在第二绝缘膜上形成浮栅。 在第一绝缘膜，浮栅和位于源极和漏极区之间的基板的那部分上形成第三绝缘膜，并且在其上不形成第二绝缘膜。 在第三绝缘膜上以与源极和漏极区相交的方向延伸的条形形成控制栅极。 在除了源极和漏极区域以及位于控制栅极下方的部分之外，在衬底中形成具有比衬底高的杂质浓度的第一导电类型的杂质区域。 浮栅晶体管构成为包括基板，源极和漏极区，第二绝缘膜，浮栅，第三绝缘膜和控制栅。 偏移晶体管构成为包括基板，源极和漏极区域，第三绝缘膜和控制栅极。 第一绝缘膜和杂质区用作存储单元的元件隔离区。

公开(公告)号：US5384742A

公开(公告)日：1995-01-24

申请号：US30343

申请日：1993-03-25

申请人： Tadashi Miyakawa ,  Masamichi Asano

发明人： Tadashi Miyakawa ,  Masamichi Asano

IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/06 ,  G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/34 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C7/00

CPC分类号： G11C16/16 ,  G11C16/10 ,  G11C16/12 ,  G11C16/3418

摘要： A memory cell array is divided into a plurality of blocks. In altering data for a block (selected block), a moderating voltage is applied to the source or control gate of a memory cell in another block (non-selected block) to moderate stress between the floating gate and source/drain, thereby preventing write error and erase error. In the program operation, the source and drain of a memory cell in the non-selected block are equalized to moderate an electric field between the control gate and source/drain and not to flow a channel current, thereby preventing write error. In carrying out a negative voltage erase method, prior to setting the source line and word line of a cell in a non-selected block to an erase voltage, the source and word lines are equalized. The equalization operation is released after the erase operation, thereby preventing malfunction of a non-selected cell.

摘要翻译： PCT No.PCT / JP91 / 01272 Sec。 371日期1993年3月25日 102（e）1993年3月25日PCT 1991年9月25日PCT公布。 出版物WO92 / 05560 日期：1992年4月2日。存储单元阵列被分成多个块。 在更改块（选择块）的数据时，将调节电压施加到另一个块（未选择块）中的存储单元的源极或控制栅极，以缓和浮动栅极和源极/漏极之间的应力，从而防止写入 错误和擦除错误。 在编程操作中，未选择的块中的存储单元的源极和漏极被均衡以控制控制栅极和源极/漏极之间的电场，并且不流过沟道电流，从而防止写入错误。 在执行负电压擦除方法时，在将未选块中的单元的源极线和字线设置为擦除电压之前，源极和字线被均衡。 在擦除操作之后释放均衡操作，从而防止未选择的单元的故障。

公开(公告)号：US5210048A

公开(公告)日：1993-05-11

申请号：US924521

申请日：1992-08-04

申请人： Atsushi Shoji ,  Masamichi Asano ,  Tadashi Miyakawa ,  Tadayuki Taura ,  Michiharu Inami

发明人： Atsushi Shoji ,  Masamichi Asano ,  Tadashi Miyakawa ,  Tadayuki Taura ,  Michiharu Inami

IPC分类号： G11C16/04 ,  H01L27/115

CPC分类号： H01L27/115 ,  G11C16/0425

摘要： Source and drain regions of a second conductivity type are formed in a stripe form in the surface area of a semiconductor substrate of a first conductivity type. A first insulation film is formed on the source and drain regions of the substrate. A second thin insulation film having a tunnel effect is formed on that part of the substrate which lies between the source and drain regions. A floating gate is formed on the second insulation film. A third insulation film is formed on the first insulation film, the floating gate and that part of the substrate which lies between the source and drain regions and on which the second insulation film is not formed. A control gate is formed on the third insulation film in a stripe form extending in a direction which intersects the source and drain regions. An impurity region of the first conductivity type having an impurity concentration higher than the substrate is formed in the substrate except the source and drain regions and the portions lying below the control gate. A floating gate transistor is constituted to include the substrate, source and drain regions, second insulation film, floating gate, third insulation film and control gate. An offset transistor is constituted to include the substrate, source and drain regions, third insulation film and control gate. The first insulation film and the impurity region are used as an element isolation region of a memory cell.

摘要翻译： 在第一导电类型的半导体衬底的表面区域中形成第二导电类型的源区和漏区。 在基板的源极和漏极区域上形成第一绝缘膜。 在位于源区和漏区之间的衬底的该部分上形成具有隧道效应的第二薄绝缘膜。 在第二绝缘膜上形成浮栅。 在第一绝缘膜，浮栅和位于源极和漏极区之间的基板的那部分上形成第三绝缘膜，并且在其上不形成第二绝缘膜。 在第三绝缘膜上以与源极和漏极区相交的方向延伸的条形形成控制栅极。 在除了源极和漏极区域以及位于控制栅极下方的部分之外，在衬底中形成具有比衬底高的杂质浓度的第一导电类型的杂质区域。 浮栅晶体管构成为包括基板，源极和漏极区，第二绝缘膜，浮栅，第三绝缘膜和控制栅。 偏移晶体管构成为包括基板，源极和漏极区域，第三绝缘膜和控制栅极。 第一绝缘膜和杂质区用作存储单元的元件隔离区。

公开(公告)号：US5095461A

公开(公告)日：1992-03-10

申请号：US457859

申请日：1989-12-27

申请人： Tadashi Miyakawa ,  Masamichi Asano

发明人： Tadashi Miyakawa ,  Masamichi Asano

IPC分类号： G11C16/14

CPC分类号： G11C16/14

摘要： An memory cell array includes a plurality of electrically erasable and programmable memory cell transistors which are arranged in a matrix form and each of which includes a source region, drain region, floating gate, erasing gate and control gate. The patterns of the control gates and the source regions in the memory cell array are arranged in parallel along the row direction of the memory cell array and the patterns of the erasing gates are arranged to extend in the column direction of the memory cell array. The memory cell transistors in the memory cell array are selected by a row decoder and a column decoder. An erasing circuit functions to erase memory data of each memory cell transistor by applying an erasing potential to the erasing gate of the memory cell transistor. A source potential generation circuit applies a first potential for programming and readout to the source region of a memory cell transistor selected by the row and column decoders when data is programmed into or read out from the selected memory cell transistor and applies a second potential which is higher than the first potential and lower than the erasing potential to the source region of each memory cell transistor when memory data of each memory cell transistor is erased by the erasing circuit. A potential difference between the source region and the erasing gate of the memory cell transistor in the erasing mode is reduced by the second potential output from the source potential generation circuit.

摘要翻译： 存储单元阵列包括以矩阵形式布置的多个电可擦除可编程存储单元晶体管，每个晶体管包括源区，漏区，浮置栅，擦除栅和控制栅。 存储单元阵列中的控制栅极和源极区域的图案沿着存储单元阵列的行方向并排布置，并且擦除栅极的图案被布置成在存储单元阵列的列方向上延伸。 存储单元阵列中的存储单元晶体管由行解码器和列解码器选择。 擦除电路用于通过向存储单元晶体管的擦除栅极施加擦除电位来擦除每个存储单元晶体管的存储器数据。 当数据被编程到所选择的存储单元晶体管中或从所选择的存储单元晶体管中读出时，源极电位产生电路将用于编程和读出的第一电位施加到由行和列解码器选择的存储单元晶体管的源极区域，并施加第二电位， 当每个存储单元晶体管的存储器数据被擦除电路擦除时，高于第一电位并且低于每个存储单元晶体管的源极区的擦除电位。 在擦除模式下存储单元晶体管的源极区域和擦除栅极之间的电位差由源极电位产生电路的第二个电位输出减小。

公开(公告)号：US5053841A

公开(公告)日：1991-10-01

申请号：US423362

申请日：1989-10-18

申请人： Tadashi Miyakawa ,  Masamichi Asano ,  Tadayuki Taura ,  Atsushi Shoji ,  Michiharu Inami

发明人： Tadashi Miyakawa ,  Masamichi Asano ,  Tadayuki Taura ,  Atsushi Shoji ,  Michiharu Inami

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/7886

摘要： A nonvolatile semiconductor memory includes a cell array in which electrically erasable programmable nonvolatile semiconductor memory cells, each using a cell transistor having source and drain regions in a semiconductor substrate, and a gate electrode with a three-layered structure on the semiconductor substrate are arranged in a matrix form. In the gate electrode having the three-layered structure, a first-layer floating gate electrode opposes a semiconductor substrate surface through a first gate insulating film, and a second- or third-layer gate electrode serves as one of erase and control gate electrodes. The erase gate electrode opposes a part of the floating gate electrode through a tunnel insulating film, and the control gate electrode opposes the floating gate electrode through a second gate insulating film. The erase and control gate electrodes are arranged to be parallel to each other, and to be perpendicular to the source and drain regions. Of two cell transistors adjacent to each other in a length direction of the channel region, the source region of one cell transistor is common to the drain region of the other cell transistor, and the cell transistors adjacent to each other in the widthwise direction of the channel region are element-isolated by an element isolation region formed in the semiconductor substrate between the channel regions.

摘要翻译： 非易失性半导体存储器包括：单元阵列，其中在半导体衬底中使用具有源极和漏极区域的单元晶体管和半导体衬底上具有三层结构的栅电极的电可擦除可编程非易失性半导体存储器单元布置在 矩阵形式。 在具有三层结构的栅电极中，第一层浮置栅电极通过第一栅极绝缘膜与半导体衬底表面相对，并且第二或第三层栅极用作擦除和控制栅电极之一。 擦除栅电极通过隧道绝缘膜与浮栅的一部分相对，并且控制栅电极通过第二栅极绝缘膜与浮栅电极相对。 擦除和控制栅电极被布置成彼此平行并且垂直于源区和漏区。 在沟道区域的长度方向上彼此相邻的两个单元晶体管中，一个单元晶体管的源极区域与另一个单元晶体管的漏极区域相同，并且在晶体管的宽度方向上彼此相邻的单元晶体管 沟道区域通过形成在沟道区域之间的半导体衬底中的元件隔离区元件隔离。

公开(公告)号：US5793696A

公开(公告)日：1998-08-11

申请号：US826820

申请日：1997-04-08

申请人： Tomoharu Tanaka ,  Masaki Momodomi ,  Hideo Kato ,  Hiroto Nakai ,  Yoshiyuki Tanaka ,  Riichiro Shirota ,  Seiichi Aritome ,  Yasuo Itoh ,  Yoshihisa Iwata ,  Hiroshi Nakamura ,  Hideko Odaira ,  Yutaka Okamoto ,  Masamichi Asano ,  Kaoru Tokushige

发明人： Tomoharu Tanaka ,  Masaki Momodomi ,  Hideo Kato ,  Hiroto Nakai ,  Yoshiyuki Tanaka ,  Riichiro Shirota ,  Seiichi Aritome ,  Yasuo Itoh ,  Yoshihisa Iwata ,  Hiroshi Nakamura ,  Hideko Odaira ,  Yutaka Okamoto ,  Masamichi Asano ,  Kaoru Tokushige

IPC分类号： G06F11/10 ,  G11C16/10 ,  G11C16/12 ,  G11C16/24 ,  G11C16/34 ,  G11C29/00 ,  G11C29/34 ,  G11C29/52 ,  G11C13/00

CPC分类号： G11C29/785 ,  G06F11/1008 ,  G11C16/10 ,  G11C16/12 ,  G11C16/24 ,  G11C16/3436 ,  G11C16/344 ,  G11C16/3454 ,  G11C29/34 ,  G11C29/52 ,  G06F11/1068 ,  G06F2201/81 ,  G06F2212/2022

摘要： The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite oepration, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.

公开(公告)号：US5615165A

公开(公告)日：1997-03-25

申请号：US576564

申请日：1995-12-21

申请人： Tomoharu Tanaka ,  Masaki Momodomi ,  Hideo Kato ,  Hiroto Nakai ,  Yoshiyuki Tanaka ,  Riichiro Shirota ,  Seiichi Aritome ,  Yasuo Itoh ,  Yoshihisa Iwata ,  Hiroshi Nakamura ,  Hideko Odaira ,  Yutaka Okamoto ,  Masamichi Asano ,  Kaoru Tokushige

发明人： Tomoharu Tanaka ,  Masaki Momodomi ,  Hideo Kato ,  Hiroto Nakai ,  Yoshiyuki Tanaka ,  Riichiro Shirota ,  Seiichi Aritome ,  Yasuo Itoh ,  Yoshihisa Iwata ,  Hiroshi Nakamura ,  Hideko Odaira ,  Yutaka Okamoto ,  Masamichi Asano ,  Kaoru Tokushige

IPC分类号： G06F11/10 ,  G11C16/10 ,  G11C16/12 ,  G11C16/24 ,  G11C16/34 ,  G11C29/00 ,  G11C29/34 ,  G11C29/52 ,  G11C13/00

CPC分类号： G11C29/785 ,  G06F11/1008 ,  G11C16/10 ,  G11C16/12 ,  G11C16/24 ,  G11C16/3436 ,  G11C16/344 ,  G11C16/3454 ,  G11C29/34 ,  G11C29/52 ,  G06F11/1068 ,  G06F2201/81 ,  G06F2212/2022

摘要： The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite operation, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.

摘要翻译： 可以缩短程序验证和擦除验证操作所需的时间。 即使重复执行写入和擦除操作，也可以抑制存储单元的阈值变化。 在编程和擦除操作之后，可以根据每个位线上的电位的预充电之后的所有位线同时判断操作，而不改变列地址。 在数据重写操作中，通过改变数据寄存器中的数据，对具有一次适当写入的数据的存储单元不进行重写操作。

公开(公告)号：US5420822A

公开(公告)日：1995-05-30

申请号：US218629

申请日：1994-03-28

申请人： Hideo Kato ,  Nobutake Sugiura ,  Kiyotaka Uchigane ,  Masamichi Asano

发明人： Hideo Kato ,  Nobutake Sugiura ,  Kiyotaka Uchigane ,  Masamichi Asano

IPC分类号： G11C8/08 ,  G11C16/16 ,  G11C16/28 ,  G11C16/34 ,  G11C29/50 ,  G11C7/00

CPC分类号： G11C16/345 ,  G11C16/16 ,  G11C16/28 ,  G11C16/344 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/50012 ,  G11C8/08 ,  G06F2201/81 ,  G11C16/04 ,  G11C2029/5004

摘要： When an erase voltage is applied to the sources of data erasable and rewritable memory cells each having a floating gate, the erasure characteristics of the memory cells can be improved by controlling the rise time of the erase voltage or by increasing the erase voltage stepwise. In test mode, no row lines are selected by a row decoder and further the sources of the respective memory cells are set to ground level. Under these conditions, in case there exists an overerased memory cell, this cell is turned on due to depletion, so that it is possible to detect the presence of the overerased memory cell on the basis of change in potential of the column line connected to this turned on memory cell. A differential amplifier is used to detect the change in potential of the column line. In the test mode, the potential of the column lines is compared with a reference potential applied to a dummy column line, and a source bias generating circuit applies a test potential suitable for test to the respective sources of the cells, to shift the threshold level of the respective cells in a positive direction, for instance. By applying this test potential to the cells, it is possible to detect the pseudo-threshold level shifted in the positive direction; that is, to detect the overerased status of the memory cell more properly.

摘要翻译： 当擦除电压施加到每个具有浮动栅极的数据可擦除和可重写存储单元的源时，可以通过控制擦除电压的上升时间或逐步增加擦除电压来提高存储器单元的擦除特性。 在测试模式下，行解码器不选择行行，并且进一步将各存储单元的源设置为地电平。 在这些条件下，在存在过度存储单元的情况下，该单元由于耗尽而导通，从而可以基于连接到该存储单元的列线的电位变化来检测过度存储存储单元的存在 打开内存单元。 差分放大器用于检测列线的电位变化。 在测试模式中，将列线的电位与施加到虚拟列线的参考电位进行比较，并且源偏置产生电路将适合于测试的测试电位施加到单元的各个源，以将阈值电平 例如，各个单元的正方向。 通过将该测试电位施加到单元，可以检测正向偏移的伪阈值电平; 也就是说，更正确地检测存储器单元的过渡状态。