公开(公告)号：US20210313455A1

公开(公告)日：2021-10-07

申请号：US17352507

申请日：2021-06-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Chung Wang ,  Chao-Ching Cheng ,  Tzu-Chiang Chen ,  Tung Ying Lee

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L29/78 ,  H01L29/423 ,  H01L29/775 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/8234

Abstract: The current disclosure describes techniques for forming a low resistance junction between a source/drain region and a nanowire channel region in a gate-all-around FET device. A semiconductor structure includes a substrate, multiple separate semiconductor nanowire strips vertically stacked over the substrate, a semiconductor epitaxy region adjacent to and laterally contacting each of the multiple separate semiconductor nanowire strips, a gate structure at least partially over the multiple separate semiconductor nanowire strips, and a dielectric structure laterally positioned between the semiconductor epitaxy region and the gate structure. The first dielectric structure has a hat-shaped profile.

公开(公告)号：US11038043B2

公开(公告)日：2021-06-15

申请号：US16396405

申请日：2019-04-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chao-Ching Cheng ,  Hung-Li Chiang ,  Tzu-Chiang Chen ,  I-Sheng Chen

IPC: H01L29/66 ,  H01L29/08 ,  H01L21/311 ,  H01L21/02 ,  H01L29/165 ,  H01L29/06 ,  H01L27/088 ,  H01L29/423 ,  H01L21/308 ,  H01L21/265 ,  H01L29/10

Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed over a bottom fin structure. A sacrificial gate structure having sidewall spacers is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is removed. The second semiconductor layers are laterally recessed. Dielectric inner spacers are formed on lateral ends of the recessed second semiconductor layers. The first semiconductor layers are laterally recessed. A source/drain epitaxial layer is formed to contact lateral ends of the recessed first semiconductor layer. The second semiconductor layers are removed thereby releasing the first semiconductor layers in a channel region. A gate structure is formed around the first semiconductor layers.

公开(公告)号：US10991811B2

公开(公告)日：2021-04-27

申请号：US16528768

申请日：2019-08-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Ching Cheng ,  Wei-Sheng Yun ,  Shao-Ming Yu ,  Tsung-Lin Lee ,  Chih-Chieh Yeh

IPC: H01L29/66 ,  H01L21/762 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786 ,  B82Y10/00 ,  H01L29/08 ,  H01L27/06 ,  H01L27/092 ,  H01L21/822 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/40 ,  H01L29/165

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a plurality of nanowires over an input-output region, and a protective layer surrounding the nanowires. The protective layer is made of silicon, silicon germanium, silicon oxide, silicon nitride, silicon sulfide, or a combination thereof. The semiconductor device structure also includes a high-k dielectric layer surrounding the protective layer, and a gate electrode surrounding the high-k dielectric layer. The semiconductor device structure further includes a source/drain portion adjacent to the gate electrode, and an interlayer dielectric layer over the source/drain portion.

公开(公告)号：US20210119131A1

公开(公告)日：2021-04-22

申请号：US16656583

申请日：2019-10-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Timothy Vasen ,  Chao-Ching Cheng ,  Matthias Passlack ,  Martin Christopher Holland ,  Tse-An Chen ,  Lain-Jong Li

IPC: H01L51/00 ,  H01L51/05

Abstract: A field effect transistor includes a semiconductor substrate, a first pad layer, carbon nanotubes and a gate structure. The first pad layer is disposed over the semiconductor substrate and comprises a 2D material. The carbon nanotubes are disposed over the first insulating pad layer. The gate structure is disposed over the semiconductor substrate and is vertically stacked with the carbon nanotubes. The carbon nanotubes extend from one side to an opposite side of the gate structure.

公开(公告)号：US20210083082A1

公开(公告)日：2021-03-18

申请号：US16573892

申请日：2019-09-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Ching Cheng ,  Hung-Li Chiang ,  Chun-Chieh Lu ,  Ming-Yang Li ,  Tzu- Chiang Chen

IPC: H01L29/76 ,  H01L29/78 ,  H01L29/45 ,  H01L29/66 ,  H01L29/20 ,  H01L29/04

Abstract: A process is provided to fabricate a finFET device having a semiconductor layer of a two-dimensional “2D” semiconductor material. The semiconductor layer of the 2D semiconductor material is a thin film layer formed over a dielectric fin-shaped structure. The 2D semiconductor layer extends over at least three surfaces of the dielectric fin structure, e.g., the upper surface and two sidewall surfaces. A vertical protrusion metal structure, referred to as “metal fin structure”, is formed about an edge of the dielectric fin structure and is used as a seed to grow the 2D semiconductor material.

公开(公告)号：US20210035633A1

公开(公告)日：2021-02-04

申请号：US16805872

申请日：2020-03-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Li Chiang ,  Chao-Ching Cheng ,  Tzu-Chiang Chen ,  Yu-Sheng Chen ,  Hon-Sum Philip Wong

IPC: G11C13/00 ,  H01L27/24

Abstract: A memory device that includes at least one memory cell is introduced. Each of the at least one memory cell is coupled to a bit line and a word line. Each of the at least one memory cell includes a memory element and a selector element, in which the memory element is configured to store data of the at least one memory cell. The selector element is coupled to the memory element in series and is configured to select the memory element for a read operation and amplify the data stored in the memory element in the read operation.

公开(公告)号：US10818777B2

公开(公告)日：2020-10-27

申请号：US16837853

申请日：2020-04-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng Chiang ,  Chen-Feng Hsu ,  Chao-Ching Cheng ,  Tzu-Chiang Chen ,  Tung Ying Lee ,  Wei-Sheng Yun ,  Yu-Lin Yang

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/06 ,  H01L29/775 ,  H01L29/08 ,  H01L29/165 ,  H01L29/78 ,  H01L21/8238 ,  B82Y10/00 ,  H01L21/02 ,  H01L21/3105

Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. A lateral end of each of the first semiconductor layers has a V-shape cross section after the first semiconductor layers are laterally etched.

公开(公告)号：US10651314B2

公开(公告)日：2020-05-12

申请号：US16235987

申请日：2018-12-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： I-Sheng Chen ,  Chao-Ching Cheng ,  Tzu-Chiang Chen ,  Carlos H. Diaz

IPC: H01L29/786 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06

Abstract: A nanowire FET device includes a vertical stack of nanowire strips configured as the semiconductor body. One or more of the top nanowire strips are receded and are shorter than the rest of the nanowire strips stacked lower. Inner spacers are uniformly formed adjacent to the receded nanowire strips and the rest of the nanowire strips. Source/drain structures are formed outside the inner spacers and a gate structure is formed inside the inner spacers, which wraps around the nanowire strips.

公开(公告)号：US20200075718A1

公开(公告)日：2020-03-05

申请号：US16598275

申请日：2019-10-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Chung Wang ,  Chao-Ching Cheng ,  Tzu-Chiang Chen ,  Tung Ying Lee

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/775 ,  H01L29/423 ,  H01L29/10 ,  H01L29/08

Abstract: The current disclosure describes techniques for forming a low resistance junction between a source/drain region and a nanowire channel region in a gate-all-around FET device. A semiconductor structure includes a substrate, multiple separate semiconductor nanowire strips vertically stacked over the substrate, a semiconductor epitaxy region adjacent to and laterally contacting each of the multiple separate semiconductor nanowire strips, a gate structure at least partially over the multiple separate semiconductor nanowire strips, and a dielectric structure laterally positioned between the semiconductor epitaxy region and the gate structure. The first dielectric structure has a hat-shaped profile.

公开(公告)号：US10134640B1

公开(公告)日：2018-11-20

申请号：US15652628

申请日：2017-07-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Li Chiang ,  I-Sheng Chen ,  Tzu-Chiang Chen ,  Chao-Ching Cheng ,  Chih-Chieh Yeh ,  Yee-Chia Yeo

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/423 ,  H01L29/06 ,  H01L29/78 ,  H01L29/786 ,  H01L27/092 ,  H01L21/02

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base portion and a fin portion over the base portion. The semiconductor device structure includes a gate structure over the fin portion and extending across the fin portion. The semiconductor device structure includes a first semiconductor wire over the fin portion and passing through the gate structure. The semiconductor device structure includes a second semiconductor wire over the first semiconductor wire and passing through the gate structure. The gate structure surrounds the second semiconductor wire and separates the first semiconductor wire from the second semiconductor wire. The first semiconductor wire and the second semiconductor wire are made of different materials.