公开(公告)号：US20220359299A1

公开(公告)日：2022-11-10

申请号：US17813850

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Ting Ko ,  Tai-Chun Huang ,  Jr-Hung Li ,  Tze-Liang Lee ,  Chi On Chui

IPC: H01L21/8234 ,  H01L29/66 ,  H01L27/088

Abstract: A method includes forming a semiconductor fin protruding higher than top surfaces of isolation regions. The isolation regions extend into a semiconductor substrate. A portion of the semiconductor fin is etched to form a trench, which extends lower than bottom surfaces of the isolation regions, and extends into the semiconductor substrate. The method further includes filling the trench with a first dielectric material to form a first fin isolation region, recessing the first fin isolation region to form a first recess, and filling the first recess with a second dielectric material. The first dielectric material and the second dielectric material in combination form a second fin isolation region.

公开(公告)号：US11417748B2

公开(公告)日：2022-08-16

申请号：US16735660

申请日：2020-01-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Ting Ko ,  Bi-Fen Wu ,  Chi-On Chui

IPC: H01L29/49 ,  H01L21/28 ,  H01L21/3215 ,  H01L21/8234 ,  H01L27/088

Abstract: A semiconductor device including a gate structure disposed on a substrate is provided. The gate structure includes a work function setting layer and a work function tuning layer sequentially disposed on substrate. The work function tuning layer is in contact with an interface surface positioned between the work function setting layer and the work function tuning layer, and a material of the interface surface is different from the work function setting layer.

公开(公告)号：US11316047B2

公开(公告)日：2022-04-26

申请号：US16662922

申请日：2019-10-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Ting Ko ,  Bo-Cyuan Lu ,  Jr-Hung Li ,  Chi-On Chui

IPC: H01L21/768 ,  H01L21/02 ,  H01L29/78 ,  H01L23/535 ,  H01L29/04 ,  H01L29/165 ,  H01L29/08 ,  H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/51

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate. The method includes forming a gate structure over the substrate. The gate structure has a first sidewall. The method includes forming a spacer element over the first sidewall of the gate structure. The method includes forming a source/drain portion adjacent to the spacer element and the gate structure. The source/drain portion has a first top surface. The method includes depositing an etch stop layer over the first top surface of the source/drain portion. The etch stop layer is made of nitride. The method includes forming a dielectric layer over the etch stop layer. The dielectric layer has a second sidewall and a bottom surface, the etch stop layer is in direct contact with the bottom surface, and the spacer element is in direct contact with the second sidewall.

公开(公告)号：US20220102152A1

公开(公告)日：2022-03-31

申请号：US17038499

申请日：2020-09-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Ju Chen ,  Chung-Ting Ko ,  Wan-Chen Hsieh ,  Chun-Ming Lung ,  Tai-Chun Huang ,  Chi On Chui

IPC: H01L21/308 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3065 ,  H01L29/66 ,  H01L21/8238

Abstract: A method includes forming a semiconductor layer over a substrate; etching a portion of the semiconductor layer to form a first recess and a second recess; forming a first masking layer over the semiconductor layer; performing a first thermal treatment on the first masking layer, the first thermal treatment densifying the first masking layer; etching the first masking layer to expose the first recess; forming a first semiconductor material in the first recess; and removing the first masking layer.

公开(公告)号：US20210134971A1

公开(公告)日：2021-05-06

申请号：US16735660

申请日：2020-01-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Ting Ko ,  Bi-Fen Wu ,  Chi-On Chui

IPC: H01L29/49 ,  H01L27/088 ,  H01L21/28 ,  H01L21/3215 ,  H01L21/8234

Abstract: A semiconductor device including a gate structure disposed on a substrate is provided. The gate structure includes a work function setting layer and a work function tuning layer sequentially disposed on substrate. The work function tuning layer is in contact with an interface surface positioned between the work function setting layer and the work function tuning layer, and a material of the interface surface is different from the work function setting layer.

公开(公告)号：US10825737B2

公开(公告)日：2020-11-03

申请号：US16242720

申请日：2019-01-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun Lee ,  Chung-Ting Ko ,  Chen-Ming Lee ,  Mei-Yun Wang ,  Fu-Kai Yang

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/768 ,  H01L23/532 ,  H01L21/285 ,  H01L29/66 ,  H01L23/485 ,  H01L29/417 ,  H01L23/522 ,  H01L23/528

Abstract: A method for semiconductor fabrication includes providing a device structure having an isolation structure, a fin adjacent the isolation structure, gate structures over the fin and the isolation structure, one or more dielectric layers over the isolation structure and the fin and between the gate structures, a first contact hole over the fin, and a second contact hole over the isolation structure. The method further includes depositing a protection layer and treating it with a plasma so that the protection layer in the first contact hole and the protection layer in the second contact hole have different etch selectivity in an etching process; and etching the protection layer to etch through the protection layer on the bottom surface of the first contact hole without etching through the protection layer on the bottom surface of the second contact hole.

公开(公告)号：US10763104B2

公开(公告)日：2020-09-01

申请号：US15874618

申请日：2018-01-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Ting Ko ,  Jr-Hung Li ,  Chi On Chui

IPC: H01L21/02 ,  H01L21/3105 ,  H01L27/092 ,  H01L21/768 ,  H01L29/66 ,  H01L21/762 ,  H01L29/423 ,  H01L29/78

Abstract: Methods of forming a differential layer, such as a Contact Etch Stop Layer (CESL), in a semiconductor device are described herein, along with structures formed by the methods. In an embodiment, a structure includes an active area on a substrate, a gate structure over the active area, a gate spacer along a sidewall of the gate structure, and a differential etch stop layer. The differential etch stop layer has a first portion along a sidewall of the gate spacer and has a second portion over an upper surface of the source/drain region. A first thickness of the first portion is in a direction perpendicular to the sidewall of the gate spacer, and a second thickness of the second portion is in a direction perpendicular to the upper surface of the source/drain region. The second thickness is greater than the first thickness.

公开(公告)号：US10510612B2

公开(公告)日：2019-12-17

申请号：US16203814

申请日：2018-11-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Cyuan Lu ,  Chunyao Wang ,  Jr-Hung Li ,  Chung-Ting Ko ,  Chi On Chui

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L29/423 ,  H01L29/417

Abstract: Gate structures and gate spacers, along with methods of forming such, are described. In an embodiment, a structure includes an active area on a substrate, a gate structure on the active area and over the substrate, and a low-k gate spacer on the active area and along a sidewall of the gate structure. The gate structure includes a conformal gate dielectric on the active area and includes a gate electrode over the conformal gate dielectric. The conformal gate dielectric extends vertically along a first sidewall of the low-k gate spacer. In some embodiments, the low-k gate spacer can be formed using a selective deposition process after a dummy gate structure has been removed in a replacement gate process.

公开(公告)号：US12272553B2

公开(公告)日：2025-04-08

申请号：US18358476

申请日：2023-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Ting Ko ,  Tai-Chun Huang ,  Chi On Chui

IPC: H01L21/027 ,  G03F7/09 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

Abstract: A method includes forming an etching mask, which includes forming a bottom anti-reflective coating over a target layer, forming an inorganic middle layer over the bottom anti-reflective coating, and forming a patterned photo resist over the inorganic middle layer. The patterns of the patterned photo resist are transferred into the inorganic middle layer and the bottom anti-reflective coating to form a patterned inorganic middle layer and a patterned bottom anti-reflective coating, respectively. The patterned inorganic middle layer is then removed. The target layer is etched using the patterned bottom anti-reflective coating to define a pattern in the target layer.

公开(公告)号：US12166076B2

公开(公告)日：2024-12-10

申请号：US17402930

申请日：2021-08-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jen-Hong Chang ,  Yi-Hsiu Liu ,  You-Ting Lin ,  Chih-Chung Chang ,  Kuo-Yi Chao ,  Jiun-Ming Kuo ,  Yuan-Ching Peng ,  Sung-En Lin ,  Chia-Cheng Chao ,  Chung-Ting Ko

IPC: H01L33/62 ,  H01L21/768 ,  H01L25/075 ,  H01L27/12 ,  H01L29/06 ,  H01L29/786

Abstract: A semiconductor device includes a first channel region, a second channel region, and a first insulating fin, the first insulating fin being interposed between the first channel region and the second channel region. The first insulating fin includes a lower portion and an upper portion. The lower portion includes a fill material. The upper portion includes a first dielectric layer on the lower portion, the first dielectric layer being a first dielectric material, a first capping layer on the first dielectric layer, the first capping layer being a second dielectric material, the second dielectric material being different than the first dielectric material, and a second dielectric layer on the first capping layer, the second dielectric layer being the first dielectric material.