公开(公告)号：US11282942B2

公开(公告)日：2022-03-22

申请号：US16925703

申请日：2020-07-10

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wei-Chih Kao ,  Hsin-Che Chiang ,  Yu-San Chien ,  Chun-Sheng Liang ,  Kuo-Hua Pan

IPC分类号： H01L29/66 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/033 ,  H01L29/78 ,  H01L29/06 ,  H01L21/762 ,  H01L21/324 ,  H01L21/768

摘要： An embodiment method includes: forming a semiconductor liner layer on exposed surfaces of a fin structure that extends above a dielectric isolation structure disposed over a substrate; forming a first capping layer to laterally surround a bottom portion of the semiconductor liner layer; forming a second capping layer over an upper portion of the semiconductor liner layer; and annealing the fin structure having the semiconductor liner layer, the first capping layer, and the second capping layer thereon, the annealing driving a dopant from the semiconductor liner layer into the fin structure, wherein a dopant concentration profile in a bottom portion of the fin structure is different from a dopant concentration profile in an upper portion of the fin structure.

公开(公告)号：US20210391327A1

公开(公告)日：2021-12-16

申请号：US16899592

申请日：2020-06-12

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yu-San Chien ,  Chun-Sheng Liang ,  Jhon-Jhy Liaw ,  Kuo-Hua Pan ,  Hsin-Che Chiang

IPC分类号： H01L27/092 ,  H01L21/8238

摘要： Provided are a semiconductor device and a method of forming the same. The semiconductor device includes a substrate, a plurality of hybrid fins, a gate, and a dielectric structure. The substrate includes a plurality of fins. The plurality of hybrid fins are respectively disposed between the plurality of fins. The gate covers portions of the plurality of fins and the plurality of hybrid fins. The dielectric structure lands on one of the plurality of hybrid fins to divide the gate into two segment. The two segments are electrically isolated to each other by the dielectric structure and the one of the plurality of hybrid fins.

公开(公告)号：US20210280711A1

公开(公告)日：2021-09-09

申请号：US17328016

申请日：2021-05-24

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yu-San Chien ,  Hsin-Che Chiang ,  Chun-Sheng Liang ,  Kuo-Hua Pan

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/768 ,  H01L21/02

摘要： An embodiment method includes forming a semiconductor liner layer on a first fin structure and on a second fin structure and forming a first capping layer on the semiconductor liner layer disposed on the first fin structure. The method further includes forming a second capping layer on the semiconductor liner layer disposed on the first fin structure, where a composition of the first capping layer is different from a composition of the second capping layer. The method additionally includes performing a thermal process on the first capping layer, the second capping layer, and the semiconductor liner layer to form a first channel region in the first fin structure and a second channel region in the second fin structure. A concentration profile of a material of the first channel region is different from a concentration profile of a material of the second channel region.

公开(公告)号：US20210234013A1

公开(公告)日：2021-07-29

申请号：US17232644

申请日：2021-04-16

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ming-Chia Tai ,  Ju-Yuan Tzeng ,  Hsin-Che Chiang ,  Yuan-Sheng Huang ,  Chun-Sheng Liang

IPC分类号： H01L29/417 ,  H01L29/66 ,  H01L21/3065 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/78

摘要： A method of applying and then removing a protective layer over a portion of a gate stack is provided. The protective layer is deposited and then a plasma precursor is separated into components. Neutral radicals are then utilized in order to remove the protective layer. In some embodiments the removal also forms a protective by-product which helps to protect underlying layers from damage during the etching process.

公开(公告)号：US11031500B2

公开(公告)日：2021-06-08

申请号：US16287368

申请日：2019-02-27

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ju-Li Huang ,  Chun-Sheng Liang ,  Ming-Hsi Yeh ,  Ying-Liang Chuang ,  Hsin-Che Chiang ,  Chun-Ming Yang ,  Yu-Chi Pan

IPC分类号： H01L29/78 ,  H01L29/423 ,  H01L21/285 ,  H01L29/40 ,  H01L21/3213 ,  H01L29/49

摘要： The present disclosure describes structure and method of a fin field-effect transistor (finFET) device. The finFET device includes: a substrate, a fin over the substrate, and a gate structure over the fin. The gate structure includes a work-function metal (WFM) layer over an inner sidewall of the gate structure. A topmost surface of the WFM layer is lower than a top surface of the gate structure. The gate structure also includes a filler gate metal layer over the topmost surface of the WFM layer. A top surface of the filler gate metal layer is substantially co-planar with the top surface of the gate structure. The gate structure further includes a self-assembled monolayer (SAM) between the filler gate metal layer and the WFM layer.

公开(公告)号：US10854506B2

公开(公告)日：2020-12-01

申请号：US16224155

申请日：2018-12-18

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Chun-Sheng Liang ,  Wei-Chih Kao ,  Hsin-Che Chiang ,  Kuo-Hua Pan

IPC分类号： H01L23/522 ,  H01L23/528 ,  H01L29/49 ,  H01L29/78 ,  H01L21/768 ,  H01L29/66 ,  H01L27/088 ,  H01L27/12 ,  H01L21/8234

摘要： A semiconductor device includes a substrate, a gate stack over the substrate, an insulating structure over the gate stack, a conductive via in the insulating structure, and an contact etch stop layer (CESL) over the insulating structure. The insulating structure has an air slit therein. The conductive via is electrically connected to the gate stack. A portion of the CESL is exposed in the air slit.

公开(公告)号：US10755970B2

公开(公告)日：2020-08-25

申请号：US16009519

申请日：2018-06-15

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsin-Che Chiang ,  Ju-Li Huang ,  Chun-Sheng Liang ,  Jeng-Ya David Yeh

IPC分类号： H01L29/76 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L29/417 ,  H01L21/311

摘要： In one exemplary aspect, a method for semiconductor manufacturing comprises forming first and second silicon nitride features on sidewall surfaces of a contact hole, where the contact hole is disposed in a dielectric layer and above a source/drain (S/D) feature. The method further comprises forming a contact plug in the contact hole, the contact plug being electrically coupled to the S/D feature, removing a top portion of the contact plug to create a recess in the contact hole, forming a hard mask layer in the recess, and removing the first and second silicon nitride features via selective etching to form first and second air gaps, respectively.

公开(公告)号：US10741558B2

公开(公告)日：2020-08-11

申请号：US16357682

申请日：2019-03-19

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsin-Che Chiang ,  Chun-Sheng Liang ,  Kuo-Hua Pan

IPC分类号： H01L27/092 ,  H01L29/78 ,  H01L29/16 ,  H01L29/24 ,  H01L29/49 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/06

摘要： A method of forming a semiconductor device includes providing a fin extruding from a substrate, the fin having first epitaxial layers alternating with second epitaxial layers, the first epitaxial layers including a first semiconductor material, the second epitaxial layers including a second semiconductor material different from the first semiconductor material; etching sidewalls of at least one of the second epitaxial layers in a channel region of the fin, such that a width of the at least one of the second epitaxial layers in the channel region after etching is smaller than a width of the first epitaxial layers contacting the at least one of the second epitaxial layers; and forming a gate stack over of the fin, the gate stack engaging both the first epitaxial layers and the second epitaxial layers.

公开(公告)号：US10475895B2

公开(公告)日：2019-11-12

申请号：US15628740

申请日：2017-06-21

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Hsin-Che Chiang ,  Ju-Yuan Tzeng ,  Chun-Sheng Liang ,  Shu-Hui Wang ,  Chih-Yang Yeh ,  Jeng-ya David Yeh

IPC分类号： H01L21/82 ,  H01L21/8234 ,  H01L21/768 ,  H01L29/423 ,  H01L29/49 ,  H01L27/088 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/8238

摘要： A semiconductor device includes a substrate, a first dielectric layer, a first device and a second device. The first dielectric layer is disposed on the substrate. The first device is disposed on the first dielectric layer on a first region of the substrate, and includes two first spacers, a second dielectric layer and a first gate structure. The first spacers are separated to form a first trench. The second dielectric layer is disposed on side surfaces and a bottom surface of the first trench. The first gate structure is disposed on the second dielectric layer. The second device is disposed on a second region of the substrate, and includes two second spacers and a second gate structure. The second spacers are disposed on the first dielectric layer and are separated to form a second trench. The second gate structure is disposed on the substrate within the second trench.

公开(公告)号：US10128156B1

公开(公告)日：2018-11-13

申请号：US15825513

申请日：2017-11-29

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Hsin-Che Chiang ,  Wen-Li Chiu ,  Chun-Sheng Liang ,  Jeng-Ya David Yeh

IPC分类号： H01L21/8234 ,  H01L27/088 ,  H01L29/51 ,  H01L29/66 ,  H01L29/06

摘要： A FinFET device and a method for fabricating the same are provided. In the method for fabricating the FinFET device, at first, a semiconductor substrate having fin structures is provided. Then, a dielectric layer and a dummy gate structure are sequentially formed on the semiconductor substrate. The dummy gate structure includes two dummy gate stacks, a gate isolation structure formed between and adjoining the dummy gate stacks, and two spacers sandwiching the dummy gate stacks and the gate isolation structure. Then, the dummy gate stacks are removed to expose portions of the dielectric layer and to expose sidewalls of portions of the spacers. Thereafter, an oxidizing treatment is conducted on the exposed portions of the dielectric layer and the portions of the spacers to increase quality of the dielectric layer.