公开(公告)号：US11264380B2

公开(公告)日：2022-03-01

申请号：US16112943

申请日：2018-08-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hou-Ju Li ,  Chur-Shyang Fu ,  Chun-Sheng Liang ,  Jeng-Ya David Yeh

IPC: H01L27/088 ,  H01L29/08 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/3105 ,  H01L21/3213

Abstract: A semiconductor device includes a substrate, a first active fin, a second active fin, a dummy fin and a first gate structure. The first and the second active fin are on the substrate and extend along a first direction. The dummy fin is disposed between the first active fin and the second active fin, and extends in the first direction. The dummy fin includes a plurality of layers, and each of the layers includes a material different from another layer. The first gate structure crosses over the dummy fin, the first and the second active fins.

公开(公告)号：US20190385896A1

公开(公告)日：2019-12-19

申请号：US16009519

申请日：2018-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Che Chiang ,  Ju-Li Huang ,  Chun-Sheng Liang ,  Jeng-Ya David Yeh

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L29/417

Abstract: In one exemplary aspect, a method for semiconductor manufacturing comprises forming first and second silicon nitride features on sidewall surfaces of a contact hole, where the contact hole is disposed in a dielectric layer and above a source/drain (S/D) feature. The method further comprises forming a contact plug in the contact hole, the contact plug being electrically coupled to the S/D feature, removing a top portion of the contact plug to create a recess in the contact hole, forming a hard mask layer in the recess, and removing the first and second silicon nitride features via selective etching to form first and second air gaps, respectively.

公开(公告)号：US10164065B1

公开(公告)日：2018-12-25

申请号：US15629862

申请日：2017-06-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsin-Che Chiang ,  Ju-Yuan Tzeng ,  Chun-Sheng Liang ,  Shu-Hui Wang ,  Chih-Yang Yeh ,  Jeng-Ya David Yeh

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/423

Abstract: In a method for manufacturing a semiconductor device, a first raised structure is formed on a surface of a substrate. The first raised structure includes a top surface and a side surface adjoining the top surface. The side surface includes an upper portion, a middle portion, and a lower portion. A deposition operation is performed with a precursor to form a first film on the top surface, the upper portion and the lower portion of the side surface, and the surface of the substrate. Performing the deposition operation includes controlling a saturated vapor pressure of the precursor. A re-deposition operation is performed on the first film and the first raised structure, so as to form a film structure. A thickness of the film structure on the middle portion of the side surface is smaller than a thickness of the film structure on the top surface.

公开(公告)号：US10755970B2

公开(公告)日：2020-08-25

申请号：US16009519

申请日：2018-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Che Chiang ,  Ju-Li Huang ,  Chun-Sheng Liang ,  Jeng-Ya David Yeh

IPC: H01L29/76 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L29/417 ,  H01L21/311

Abstract: In one exemplary aspect, a method for semiconductor manufacturing comprises forming first and second silicon nitride features on sidewall surfaces of a contact hole, where the contact hole is disposed in a dielectric layer and above a source/drain (S/D) feature. The method further comprises forming a contact plug in the contact hole, the contact plug being electrically coupled to the S/D feature, removing a top portion of the contact plug to create a recess in the contact hole, forming a hard mask layer in the recess, and removing the first and second silicon nitride features via selective etching to form first and second air gaps, respectively.

公开(公告)号：US10734283B2

公开(公告)日：2020-08-04

申请号：US16049305

申请日：2018-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hui-Chi Chen ,  Hsiang-Ku Shen ,  Jeng-Ya David Yeh

IPC: H01L29/78 ,  H01L21/768 ,  H01L29/66

Abstract: A semiconductor device includes a first gate structure disposed on a substrate and extending in a first direction. The first gate structure includes a first gate electrode, a first cap insulating layer disposed over the first gate electrode, first sidewall spacers disposed on opposing side faces of the first gate electrode and the first cap insulating layer and second sidewall spacers disposed over the first sidewall spacers. The semiconductor device further includes a first protective layer formed over the first cap insulating layer, the first sidewall spacers and the second sidewall spacers. The first protective layer has a π-shape having a head portion and two leg portions in a cross section along a second direction perpendicular to the first direction.

公开(公告)号：US10134872B2

公开(公告)日：2018-11-20

申请号：US15063346

申请日：2016-03-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yao-De Chiou ,  Janet Chen ,  Jeng-Ya David Yeh

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L21/8238 ,  H01L21/8234

Abstract: In a method of manufacturing a semiconductor device, a dummy gate structure is formed over a substrate. A source/drain region is formed. A first insulating layer is formed over the dummy gate structure and the source/drain region. A gate space is formed by removing the dummy gate structure. The gate space is filled with a first metal layer. A gate recess is formed by removing an upper portion of the filled first metal layer. A second metal layer is formed over the first metal layer in the gate recess. A second insulating layer is formed over the second metal layer in the gate recess.

公开(公告)号：US10128156B1

公开(公告)日：2018-11-13

申请号：US15825513

申请日：2017-11-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsin-Che Chiang ,  Wen-Li Chiu ,  Chun-Sheng Liang ,  Jeng-Ya David Yeh

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/51 ,  H01L29/66 ,  H01L29/06

Abstract: A FinFET device and a method for fabricating the same are provided. In the method for fabricating the FinFET device, at first, a semiconductor substrate having fin structures is provided. Then, a dielectric layer and a dummy gate structure are sequentially formed on the semiconductor substrate. The dummy gate structure includes two dummy gate stacks, a gate isolation structure formed between and adjoining the dummy gate stacks, and two spacers sandwiching the dummy gate stacks and the gate isolation structure. Then, the dummy gate stacks are removed to expose portions of the dielectric layer and to expose sidewalls of portions of the spacers. Thereafter, an oxidizing treatment is conducted on the exposed portions of the dielectric layer and the portions of the spacers to increase quality of the dielectric layer.

公开(公告)号：US09997522B2

公开(公告)日：2018-06-12

申请号：US14958769

申请日：2015-12-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jui-Yao Lai ,  Sai-Hooi Yeong ,  Yen-Ming Chen ,  Ying-Yan Chen ,  Jeng-Ya David Yeh

IPC: H01L27/11 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/535 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L27/1104 ,  H01L21/02164 ,  H01L21/31051 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823437 ,  H01L21/823475 ,  H01L23/535 ,  H01L27/088 ,  H01L29/6653

Abstract: A semiconductor device comprises a first gate electrode disposed on a substrate, a first source/drain region, and a local interconnect connecting the first gate electrode and the first source/drain region. The local interconnect is disposed between the substrate and a first metal wiring layer in which a power supply line is disposed. The local interconnect has a key hole shape in a plan view, and has a head portion, a neck portion and a body portion connected to the head portion via the neck portion. The neck portion is disposed over the first gate electrode and the body portion is disposed over the first source/drain region.

公开(公告)号：US12199164B2

公开(公告)日：2025-01-14

申请号：US18306168

申请日：2023-04-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsin-Che Chiang ,  Ju-Yuan Tzeng ,  Chun-Sheng Liang ,  Chih-Yang Yeh ,  Shu-Hui Wang ,  Jeng-Ya David Yeh

IPC: H01L29/423 ,  H01L21/28 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L29/165 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

Abstract: A method includes forming a semiconductor fin over a substrate; forming a gate structure over the semiconductor fin, the gate structure comprising: a first metallic layer; a second metallic layer over the first metallic layer, wherein the first metallic layer is a metal compound of a first element and a second element and the second metallic layer is a single-element metal of the second element; and an oxide layer between the first metallic layer and the second metallic layer.

公开(公告)号：US11670697B2

公开(公告)日：2023-06-06

申请号：US17353606

申请日：2021-06-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsin-Che Chiang ,  Ju-Yuan Tzeng ,  Chun-Sheng Liang ,  Chih-Yang Yeh ,  Shu-Hui Wang ,  Jeng-Ya David Yeh

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L21/28 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L29/165 ,  H01L29/51

CPC classification number: H01L29/42372 ,  H01L21/28088 ,  H01L21/7684 ,  H01L21/76846 ,  H01L23/5283 ,  H01L23/5329 ,  H01L23/53204 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/165 ,  H01L29/517 ,  H01L29/7843 ,  H01L29/7848

Abstract: A semiconductor device includes a substrate comprising a semiconductor fin, a gate structure over the semiconductor fin, and source/drain structures over the semiconductor fin and on opposite sides of the gate structure. The gate stack comprises a high-k dielectric layer; a first work function metal layer over the high-k dielectric layer; an oxide of the first work function metal layer over the first work function metal layer; and a second work function metal layer over the oxide of the first work function metal layer, in which the first and second work function metal layers have different compositions; and a gate electrode over the second work function metal layer.