公开(公告)号：US20210082873A1

公开(公告)日：2021-03-18

申请号：US16568623

申请日：2019-09-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ping-Tzu Chen ,  Hsing-Chih Lin ,  Min-Feng Kao

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/367 ,  H01L23/48 ,  H01L27/088 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: In some embodiments, the present disclosure relates to a three dimensional (3D) integrated circuit (IC) stack, including a first IC die having a first substrate and a first interconnect structure over a frontside of the first substrate; a second IC die having a second substrate and a second interconnect structure over the frontside of the second substrate; and a third IC die vertically between the first and second IC dies and having a third substrate, a third interconnect structure over the frontside of the third substrate, and a third bonding structure over a backside of the third substrate. A heat dissipation path extends from the third substrate to at least the first or second substrate, and includes a backside contact that extends from the third bonding structure to the backside of the third substrate and that is thermally coupled to at least the first or second interconnect structure.

公开(公告)号：US20200381512A1

公开(公告)日：2020-12-03

申请号：US16553222

申请日：2019-08-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Feng Kao ,  Dun-Nian Yaung ,  Hsing-Chih Lin ,  Jen-Cheng Liu ,  Wei-Tao Tsai

IPC: H01L29/06 ,  H01L25/065 ,  H01L23/00 ,  H01L21/768 ,  H01L21/762 ,  H01L23/48 ,  H01L23/522

Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) in which a shield structure blocks the migration of charge to a semiconductor device from proximate a through substrate via (TSV). In some embodiments, the IC comprises a substrate, an interconnect structure, the semiconductor device, the TSV, and the shield structure. The interconnect structure is on a frontside of the substrate and comprises a wire. The semiconductor device is on the frontside of the substrate, between the substrate and the interconnect structure. The TSV extends completely through the substrate, from a backside of the substrate to the wire, and comprises metal. The shield structure comprises a PN junction extending completely through the substrate and directly between the semiconductor device and the TSV.

公开(公告)号：US10804155B2

公开(公告)日：2020-10-13

申请号：US16584824

申请日：2019-09-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Han Huang ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Hsing-Chih Lin ,  Jen-Cheng Liu ,  Min-Feng Kao

IPC: H01L21/822 ,  H01L23/522 ,  H01L23/00 ,  H01L25/065 ,  H01L27/06 ,  H01F17/00 ,  H01F41/04 ,  H01L21/768 ,  H01L27/08 ,  H01L49/02

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a first conductive wire within a first dielectric structure formed on a first surface of a first substrate. A through-substrate-via (TSV) is formed to extend though the first substrate. A second conductive wire is formed within a second dielectric structure formed on a second surface of the first substrate opposing the first surface. The TSV electrically couples the first conductive wire and the second conductive wire. The first conductive wire, the second conductive wire, and the TSV define an inductor that wraps around an axis.

公开(公告)号：US20200066584A1

公开(公告)日：2020-02-27

申请号：US16600845

申请日：2019-10-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Feng Kao ,  Dun-Nian Yaung ,  Hsing-Chih Lin ,  Jen-Cheng Liu ,  Kuan-Chieh Huang

IPC: H01L21/768 ,  H01L27/088 ,  H01L21/822 ,  H01L27/06 ,  H01L23/48 ,  H01L23/522 ,  H01L21/762

Abstract: An integrated circuit (IC) provides high performance and high functional density. A first back-end-of-line (BEOL) interconnect structure and a second BEOL interconnect structure are respectively under and over a semiconductor substrate. A first electronic device and a second electronic device are between the semiconductor substrate and respectively a bottom of the first BEOL interconnect structure and a top of the second BEOL interconnect structure. A through substrate via (TSV) extends through the semiconductor substrate, from the first BEOL interconnect structure to the second BEOL interconnect structure. A method for manufacturing the IC is also provided.

公开(公告)号：US20190122931A1

公开(公告)日：2019-04-25

申请号：US15793127

申请日：2017-10-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Han Huang ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Hsing-Chih Lin ,  Jen-Cheng Liu ,  Min-Feng Kao

IPC: H01L21/822 ,  H01L49/02 ,  H01F17/00 ,  H01L27/08 ,  H01L21/768 ,  H01L23/00 ,  H01F41/04

Abstract: The present disclosure, in some embodiments, relates to an integrated circuit having an inductor with one or more turns arranged along vertical planes that intersect an underlying substrate. In some embodiments, the integrated circuit includes a plurality of conductive routing layers having conductive wires and conductive vias disposed within one or more dielectric structures abutting a first substrate. The plurality of conductive routing layers define an inductor having one or more turns respectively including a vertically extending segment arranged along a plane that intersects the first substrate. The vertically extending segment has a plurality of the conductive wires and the conductive vias.

公开(公告)号：US10157991B2

公开(公告)日：2018-12-18

申请号：US15875304

申请日：2018-01-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsing-Chih Lin

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L27/11521

Abstract: A method for fabricating a memory device is provided. The method for fabricating a memory device includes forming a first dielectric layer over a substrate and forming a floating gate layer over the first dielectric layer. The method further includes forming a hard mask layer over the floating gate layer and etching the hard mask layer to form a recess in the hard mask layer. The method further includes patterning a portion of the hard mask layer under the recess to form a recessed feature having a first tip corner and etching the recessed feature and the floating gate layer to form a floating gate having a second tip corner. The method further includes depositing a second dielectric layer over the floating gate and forming a control gate partially over the floating gate and separating from the floating gate by the second dielectric layer.

公开(公告)号：US09786592B2

公开(公告)日：2017-10-10

申请号：US14929040

申请日：2015-10-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jeng-Shyan Lin ,  Dun-Nian Yaung ,  Hsing-Chih Lin ,  Jen-Cheng Liu ,  Min-Feng Kao ,  Hsun-Ying Huang

IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L23/48 ,  H01L23/525

CPC classification number: H01L23/5226 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/522 ,  H01L23/525 ,  H01L23/528

Abstract: An integrated circuit structure with a back side through silicon via (B/S TSV) therein and a method of forming the same is disclosed. The method includes the steps of: receiving a wafer comprising a substrate having a front side that has a conductor thereon and a back side; forming a back side through silicon via (B/S TSV) from the back side of the substrate to penetrate the substrate; and filling the back side through silicon via (B/S TSV) with a conductive material to form an electrical connection with the conductor. Thus a back side through silicon via penetrates the back side of the substrate and electrically connects to the conductor on the front side of the substrate is formed.

公开(公告)号：US09620553B2

公开(公告)日：2017-04-11

申请号：US15183595

申请日：2016-06-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chien-Chang Huang ,  Hsing-Chih Lin ,  Chien-Nan Tu ,  Yu-Lung Yeh

IPC: H01L27/146

CPC classification number: H01L27/14643 ,  H01L27/1462 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/14629 ,  H01L27/1463 ,  H01L27/1464 ,  H01L27/14685 ,  H01L27/14687 ,  H01L27/14689

Abstract: A semiconductor device includes a substrate, a semiconductor layer, light-sensing devices, a transparent dielectric layer and a grid shielding layer. The semiconductor layer overlies the substrate, and has a first surface and a second surface opposite to the first surface. The semiconductor layer includes microstructures disposed on the second surface of the semiconductor layer. The light-sensing devices are disposed on the first surface of the semiconductor layer. The transparent dielectric layer is disposed on the second surface of the semiconductor layer, and covers the microstructures. The grid shielding layer extends from the first surface of the semiconductor layer toward the second surface of the semiconductor layer, and surrounds each of the light-sensing devices to separate the light-sensing devices from each other, in which a depth of the grid shielding layer is greater than two-thirds of a thickness of the semiconductor layer.

公开(公告)号：US09577189B2

公开(公告)日：2017-02-21

申请号：US14989495

申请日：2016-01-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsing-Chih Lin

IPC: H01L45/00 ,  H01L51/05 ,  H01L51/00

CPC classification number: H01L45/1273 ,  H01L45/04 ,  H01L45/06 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16 ,  H01L45/1616 ,  H01L51/0035 ,  H01L51/0591

Abstract: A method of forming an RRAM cell structure is provided. The method includes forming dummy features over a substrate, and the dummy features have a gap therebetween. The method also includes depositing an oxide layer over the dummy features while forming a first V-shaped valley on the oxide layer. The method further includes partially planarizing the oxide layer while leaving the first V-shaped valley. In addition, the method includes forming a first electrode over the oxide layer while forming a second V-shaped valley on the first electrode. The method further includes forming a resistance variable layer over the first electrode in a conformal manner. The method still includes forming a second electrode over the resistance variable layer.

Abstract translation: 提供了形成RRAM单元结构的方法。 该方法包括在衬底上形成虚拟特征，并且虚拟特征在它们之间具有间隙。 该方法还包括在虚拟特征上沉积氧化物层，同时在氧化物层上形成第一V形谷底。 该方法还包括在离开第一V形谷的同时部分地平坦化氧化物层。 此外，该方法包括在氧化物层上形成第一电极，同时在第一电极上形成第二V形谷。 该方法还包括以保形方式在第一电极上形成电阻变化层。 该方法还包括在电阻变化层上形成第二电极。