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    Level shifter
    52.
    发明授权
    Level shifter 有权

    公开(公告)号：US09979399B2

    公开(公告)日：2018-05-22

    申请号：US15073948

    申请日：2016-03-18

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Chien-Yuan Chen ,  Cheng Hung Lee ,  Hung-Jen Liao ,  Hau-Tai Shieh ,  Che-Ju Yeh

    IPC: H03L5/00 ,  H03K19/0185

    CPC classification number: H03K19/018521

    Abstract: A circuit is disclosed. The circuit includes eight MOD transistors and a capacitor, the first MOS transistor having a source coupled to a first predetermined supply voltage (VDDM), a second MOS transistor having a source coupled to a first predetermined supply voltage VDDM, a third MOS transistor having a source coupled to a drain of the first MOS transistor, a fourth MOS transistor having a source coupled to a drain of the second MOS transistor, a fifth MOS transistor having a source coupled to a drain of the third MOS transistor and a gate of the second MOS transistor, and a gate coupled to a gate of the third MOS transistor and an input node, and a drain coupled to ground, a sixth MOS transistor having a source coupled to a drain of the fourth MOS transistor and a gate of the first MOS transistor and an output node.

    Voltage supply selection circuit
    56.
    发明授权
    Voltage supply selection circuit 有权

    公开(公告)号：US11728789B2

    公开(公告)日：2023-08-15

    申请号：US17406273

    申请日：2021-08-19

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chia-Chen Kuo ,  Yangsyu Lin ,  Yu-Hao Hsu ,  Cheng Hung Lee ,  Hung-Jen Liao ,  Jonathan Tsung-Yung Chang

    IPC: H03K3/012

    CPC classification number: H03K3/012

    Abstract: The present disclosure describes an example circuit for selecting a voltage supply. The circuit includes a first control switch, a first voltage supply switch, a second control switch, and a second voltage supply switch. The first control switch is configured to receive a control signal and a first voltage supply. The first voltage supply switch is electrically coupled to the first control switch and is configured to receive a second voltage supply. The second voltage supply switch is electrically coupled to the second control switch and configured to receive the first voltage supply. The first and second voltage supply switches are configured to selectively output the first and second voltage supplies based on the control signal.

    Memory cell
    58.
    发明授权
    Memory cell 有权

    公开(公告)号：US10964389B2

    公开(公告)日：2021-03-30

    申请号：US16911049

    申请日：2020-06-24

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hidehiro Fujiwara ,  Hung-Jen Liao ,  Hsien-Yu Pan ,  Chih-Yu Lin ,  Yen-Huei Chen ,  Chien-Chen Lin

    IPC: G11C15/00 ,  G11C15/04 ,  H01L27/02 ,  G11C11/412

    Abstract: A cell structure is disclosed. The cell structure includes a first unit comprising a first group of transistors and a first data latch, a second unit comprising a second group of transistors and a second data latch a read port unit comprising a plurality of p-type transistors, a search line and a complementary search line, the search line and the complementary search line function as input of the cell structure, and a master line, the master line functions as an output of the cell structure, the first unit is coupled to the second unit, both the first and the second units are coupled to the read port unit. According to some embodiments, the first data latch comprises a first and a second p-type transistors, a first and a second n-type transistors.

    Variation tolerant read assist circuit for SRAM
    60.
    发明授权
    Variation tolerant read assist circuit for SRAM 有权

    公开(公告)号：US10832765B2

    公开(公告)日：2020-11-10

    申请号：US16376640

    申请日：2019-04-05

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hidehiro Fujiwara ,  Hung-Jen Liao ,  Hsien-Yu Pan ,  Chih-Yu Lin ,  Yen-Huei Chen ,  Sahil Preet Singh

    IPC: G11C11/419 ,  G11C11/412

    Abstract: A read assist circuit is disclosed that selectively provides read assistance to a number of memory cells during a read operation of the number of memory cells. The read assist circuit includes a voltage divider circuit and a number of write line driver circuits. The voltage divider circuit is configured to voltage-divide a power supply voltage and provide a source write line voltage at an output of the voltage divider circuit to the number of write line driver circuits. Each write line driver circuit is configured to receive the source write line voltage and selectively apply the source write line voltage to a corresponding write line according to a corresponding individual enable signal that controls each write driver circuit. Further, each write line driver circuit is coupled to a corresponding memory cell of the number of memory cells via the corresponding write line so that the corresponding write line provides a corresponding write line voltage to provide read assistance during the read operation.

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