公开(公告)号：US20120091836A1

公开(公告)日：2012-04-19

申请号：US13057875

申请日：2010-03-31

申请人： Koji Hayashi ,  Makoto Tomita ,  Shinichi Kojima ,  Ryuichi Hasegawa ,  Takahiro Miki

发明人： Koji Hayashi ,  Makoto Tomita ,  Shinichi Kojima ,  Ryuichi Hasegawa ,  Takahiro Miki

IPC分类号： H02K9/19 ,  F28F7/00

CPC分类号： H02K9/19 ,  B60L3/0061 ,  B60L11/14 ,  B60L15/2009 ,  B60L2240/12 ,  B60L2240/36 ,  B60L2240/421 ,  B60L2240/441 ,  F16H57/0412 ,  F16H57/045 ,  F16H57/0476 ,  H02K16/00 ,  H02K51/00 ,  Y02T10/641 ,  Y02T10/645 ,  Y02T10/70 ,  Y02T10/7077 ,  Y02T10/72 ,  Y02T10/7275

摘要： A heat-generating portion cooling structure of vehicle drive apparatus that sufficiently supplies cooling oil to heat-generating portions to enhance efficiency of the vehicle drive apparatus when the heat-generating portions generate maximum heat includes drawing means for drawing oil in a case into a catch tank, and an oil circulation passage for circulating the oil through the catch tank while supplying the oil to first and second heat-generating portions. The oil circulation passage includes a first passage for the oil to flow to the first heat-generating portion when the oil surface in the catch tank is at a first height and a second passage for the oil to flow to the second heat-generating portion when the oil surface is at a second height lower than the first height, and more amount of oil flows to the second heat-generating portion than to the first heat-generating portion when the oil surface is low.

摘要翻译： 当发热部产生最大热量时，将驱动装置的冷却油向发热部充分供给以提高车辆驱动装置的效率的发热部冷却结构，包括将壳体内的油抽入捕集器 罐和油循环通道，用于在将油供应到第一和第二发热部分的同时使油通过捕集罐。 油循环通道包括第一通道，用于当捕集罐中的油表面处于第一高度时油流向第一发热部分，并且第二通道用于油流到第二发热部分时， 油表面处于比第一高度低的第二高度，并且当油表面低时，更多的油流到第二发热部分而不是第一发热部分。

公开(公告)号：US07292172B2

公开(公告)日：2007-11-06

申请号：US11214723

申请日：2005-08-31

申请人： Osamu Matsumoto ,  Takahiro Miki ,  Yasuo Morimoto

发明人： Osamu Matsumoto ,  Takahiro Miki ,  Yasuo Morimoto

IPC分类号： H03M1/66

CPC分类号： H03M1/0604 ,  H03M1/742

摘要： A current driven D/A converter sets an OFF control voltage (BIAS3) for turning off NMOS transistors M12P, M12N, M22P, M22N, M32P and M32N at a voltage close to an ON control voltage (BIAS2). This makes it possible to reduce the swing of the control voltage (ON control voltage-OFF control voltage) of the NMOS transistors, and hence to reduce the noise due to charge injections through parasitic capacitances, and noise of a ground voltage or power supply voltage due to flowing of discharge currents from the parasitic capacitances to the ground or power supply at turn off of the transistors, thereby being able to offer a high performance current driven D/A converter.

摘要翻译： 电流驱动D / A转换器设置用于关闭NMOS晶体管M 12 P，M 12 N，M 22 P，M 22 N，M 32 P和M 32 N的截止控制电压（BIAS 3） ON控制电压（BIAS 2）。 这使得可以减小NMOS晶体管的控制电压（ON控制电压 - 关闭控制电压）的摆动，从而减少由于通过寄生电容的电荷注入引起的噪声，以及接地电压或电源电压的噪声 由于在晶体管截止时由寄生电容放电到地或电源的放电电流的流动，从而能够提供高性能的电流驱动D / A转换器。

公开(公告)号：US20050231404A1

公开(公告)日：2005-10-20

申请号：US11151551

申请日：2005-06-14

申请人： Hisashi Harada ,  Takahiro Miki ,  Hideo Matsui

发明人： Hisashi Harada ,  Takahiro Miki ,  Hideo Matsui

IPC分类号： H03M1/14 ,  H03M1/10 ,  H03M1/12 ,  H03M1/34 ,  H03M1/46

CPC分类号： H03M1/1225 ,  H03M1/46

摘要： A successive approximation A/D converter includes first and second S/H and comparators sampling and holding first and second external analog input voltages simultaneously and comparing the held, first and second external analog input voltages with a reference voltage to output first and second signals having levels corresponding to resultant comparisons, and a reference voltage generator operative in response to the first and second signals to generate the reference voltage. The two S/H and comparators share the single reference voltage generator. A reduced chip area can be achieved.

公开(公告)号：US06919837B2

公开(公告)日：2005-07-19

申请号：US10895090

申请日：2004-07-21

申请人： Hisashi Harada ,  Takahiro Miki ,  Hideo Matsui

发明人： Hisashi Harada ,  Takahiro Miki ,  Hideo Matsui

IPC分类号： H03M1/14 ,  H03M1/10 ,  H03M1/12 ,  H03M1/34 ,  H03M1/46

CPC分类号： H03M1/1225 ,  H03M1/46

摘要： A successive approximation A/D converter includes first and second S/H and comparators sampling and holding first and second external analog input voltages simultaneously and comparing the held, first and second external analog input voltages with a reference voltage to output first and second signals having levels corresponding to resultant comparisons, and a reference voltage generator operative in response to the first and second signals to generate the reference voltage. The two S/H and comparators share the single reference voltage generator. A reduced chip area can be achieved.

摘要翻译： 逐次逼近A / D转换器包括第一和第二S / H，并且比较器同时采样并保持第一和第二外部模拟输入电压，并将保持的，第一和第二外部模拟输入电压与参考电压进行比较，以输出具有 对应于所得比较的电平，以及响应于第一和第二信号而工作以产生参考电压的参考电压发生器。 两个S / H和比较器共享单个参考电压发生器。 可以实现减少的芯片面积。

公开(公告)号：US20050024251A1

公开(公告)日：2005-02-03

申请号：US10895090

申请日：2004-07-21

申请人： Hisashi Harada ,  Takahiro Miki ,  Hideo Matsui

发明人： Hisashi Harada ,  Takahiro Miki ,  Hideo Matsui

IPC分类号： H03M1/14 ,  H03M1/10 ,  H03M1/12 ,  H03M1/34 ,  H03M1/46

CPC分类号： H03M1/1225 ,  H03M1/46

摘要： A successive approximation A/D converter includes first and second S/H and comparators sampling and holding first and second external analog input voltages simultaneously and comparing the held, first and second external analog input voltages with a reference voltage to output first and second signals having levels corresponding to resultant comparisons, and a reference voltage generator operative in response to the first and second signals to generate the reference voltage. The two S/H and comparators share the single reference voltage generator. A reduced chip area can be achieved.

公开(公告)号：US06756812B2

公开(公告)日：2004-06-29

申请号：US10263661

申请日：2002-10-04

申请人： Hideo Nagano ,  Takahiro Miki

发明人： Hideo Nagano ,  Takahiro Miki

IPC分类号： H03K19003

CPC分类号： H04L25/0298

摘要： A differential termination resistor adjusting circuit includes: a reference current producing section that produces a nearly constant reference current Iref, a reference voltage producing section that produces nearly constant reference voltages VrefH, VrefL, a replica resistor producing section that is provided with the reference current Iref to produce voltage drops Va, Vb, a control voltage producing section that produces control voltages Vcont1, Vcont2, based on the reference voltages VrefH, VrefL and the voltage drops Va, Vb, and a genuine resistor producing section that is built in a receiving side device and is connected to an input termination, characterized in that the resistances of the replica resistor producing section and the genuine resistor producing section are adjusted by the control voltages Vcont1, Vcont2.

摘要翻译： 差分终端电阻调节电路包括：产生几乎恒定的参考电流Iref的参考电流产生部分，产生几乎恒定的参考电压VrefH，VrefL的参考电压产生部分，具有参考电流I ref的复制电阻产生部分 产生电压降Va，Vb，基于参考电压VrefH，VrefL和电压降Va，Vb产生控制电压Vcont1，Vcont2的控制电压产生部分和内置在接收侧的正电阻产生部分 并且连接到输入端子，其特征在于，通过控制电压Vcont1，Vcont2调节复制电阻产生部分和正电阻产生部分的电阻。

公开(公告)号：US5818380A

公开(公告)日：1998-10-06

申请号：US824549

申请日：1997-03-25

申请人： Masao Ito ,  Takahiro Miki ,  Shiro Hosotani

发明人： Masao Ito ,  Takahiro Miki ,  Shiro Hosotani

IPC分类号： H03M1/10 ,  H03K19/23 ,  H03M1/06 ,  H03M1/36

CPC分类号： H03M1/0602 ,  H03M1/361

摘要： A majority logic circuit is supplied with output values of adjacent three comparators. The majority logic circuit outputs, as an output signal, the supplied three output values including at least two equal output values. Inverter circuits and AND circuits produce and output a read signal of an encoder which is a logical product between the output signal and an inverted signal of the output signal.

摘要翻译： 多数逻辑电路提供相邻三个比较器的输出值。 多数逻辑电路作为输出信号输出所提供的三个输出值，包括至少两个相等的输出值。 逆变器电路和AND电路产生并输出编码器的读取信号，该编码器是输出信号和输出信号的反相信号之间的逻辑积。

公开(公告)号：US5631579A

公开(公告)日：1997-05-20

申请号：US548066

申请日：1995-10-25

申请人： Takahiro Miki ,  Hiroyuki Kouno ,  Yasuyuki Nakamura

发明人： Takahiro Miki ,  Hiroyuki Kouno ,  Yasuyuki Nakamura

IPC分类号： G06F3/00 ,  G11C11/409 ,  H01L27/02 ,  H03K19/003 ,  H03K19/0175 ,  H03K19/0185

CPC分类号： H03K19/00315 ,  H01L27/0251

摘要： An output buffer circuit operating normally when its supply potential is exceeded by the potential of the bus to which the buffer circuit output is connected. The circuit comprises a p-channel MOS transistor and a first and a second n-channel MOS transistor. The output node of the output buffer circuit is connected not to the p-channel MOS transistor but to the connection point between the source of the first n-channel MOS transistor and the drain of the second n-channel MOS transistor. The threshold potential of the first n-channel MOS transistor is set so that, with the output node in the high-impedance state, the first n-channel MOS transistor is turned off when the output node potential exceeds the supply potential of the output buffer circuit. This prevents the p-channel MOS transistor from getting activated or from being forward-biased between the back gate and the drain or source. Thus no leak current flows when the bus potential becomes higher than the supply potential of the output buffer circuit.

摘要翻译： 当缓冲电路输出的总线的电位超过其电源电位时，输出缓冲电路正常工作。 电路包括p沟道MOS晶体管和第一和第二n沟道MOS晶体管。 输出缓冲电路的输出节点不连接到p沟道MOS晶体管，而是连接到第一n沟道MOS晶体管的源极和第二n沟道MOS晶体管的漏极之间的连接点。 第一n沟道MOS晶体管的阈值电位被设置为使得当输出节点处于高阻抗状态时，当输出节点电位超过输出缓冲器的供给电位时，第一n沟道MOS晶体管截止 电路。 这防止了p沟道MOS晶体管在背栅极和漏极或源极之间被激活或被正向偏置。 因此，当总线电位变得高于输出缓冲电路的电源电位时，没有泄漏电流流动。

公开(公告)号：US5497120A

公开(公告)日：1996-03-05

申请号：US350030

申请日：1994-11-29

申请人： Masao Ito ,  Takahiro Miki

发明人： Masao Ito ,  Takahiro Miki

IPC分类号： G01R19/165 ,  H03F1/30 ,  H03F3/45 ,  H03K17/16

CPC分类号： G01R19/16519 ,  H03F1/303 ,  H03F3/45076

摘要： A differential amplifier circuit is obtained in which an operating power source voltage is suppressed to a minimum necessary level. The differential amplifier circuit includes a bias circuit having a differential amplifier with NMOS transistors (11A, 11B, 12A and 12B) and PMOS transistors (13A and 13B). Sources of NMOS transistors (11A)and (11B) are commonly grounded. A bias voltage (VB1) is supplied to gates of the NMOS transistors (11A) and (11B). Drains of the NMOS transistors (11A) and (11B) are connected to sources of NMOS transistors (12A) and (12B), respectively. A gate and a drain of the NMOS transistor (12A) are short-circuited to each other with the drain connected to a drain of a PMOS transistor (13A). A bias voltage (VB4) is applied to a gate of the NMOS transistor (12B). A drain of the NMOS transistor (12B) is connected to a drain of the PMOS transistor (13B) whose gate and drain are shared by each other. Gates of the PMOS transistors (13A) and (13B) are connected to a bias terminal (72) while sources of the PMOS transistors (13A) and (13B) are commonly connected to a power source. The bias terminal (72) is connected to an input bias terminal of a differential amplifier.

摘要翻译： 获得了将工作电源电压抑制到最小必要水平的差分放大电路。 差分放大器电路包括具有NMOS晶体管（11A，11B，12A和12B）和PMOS晶体管（13A和13B）的差分放大器的偏置电路。 NMOS晶体管（11A）和（11B）的源极通常接地。 偏置电压（VB1）被提供给NMOS晶体管（11A）和（11B）的栅极。 NMOS晶体管（11A）和（11B）的漏极分别连接到NMOS晶体管（12A）和（12B）的源极。 NMOS晶体管（12A）的栅极和漏极彼此短路，漏极连接到PMOS晶体管（13A）的漏极。 偏置电压（VB4）施加到NMOS晶体管（12B）的栅极。 NMOS晶体管（12B）的漏极连接到其栅极和漏极彼此共享的PMOS晶体管（13B）的漏极。 PMOS晶体管（13A）和（13B）的栅极连接到偏置端子（72），而PMOS晶体管（13A）和（13B）的源极共同连接到电源。 偏置端子（72）连接到差分放大器的输入偏置端子。

公开(公告)号：US5225837A

公开(公告)日：1993-07-06

申请号：US706834

申请日：1991-05-29

申请人： Shiro Hosotani ,  Takahiro Miki ,  Masao Ito

发明人： Shiro Hosotani ,  Takahiro Miki ,  Masao Ito

IPC分类号： H03M1/36 ,  H03M1/78

CPC分类号： H03M1/362

摘要： An A/D converter includes a resistor network generating a reference voltage, a level detector for detecting the level of an input analogue signal with a reference voltage from the resistor network as a reference, and an encoder for providing a digital signal by encoding the output of the level detector. The level detector includes a plurality of comparators for bilevel-processing the input analogue signal with a preselected voltage from the resistor connection nodes of the resistor network as a reference voltage. The resistor network comprises a plurality of resistor elements between a first node receiving a first reference voltage and a second node receiving a second reference voltage, which are interconnected to provide a voltage from an associated connection node that is 1/2.sup.j times the difference between said first reference voltage and said second reference voltage. The comparator includes capacitors for providing the difference between the input analogue signal and the reference voltage by a capacitor coupling, and an inverter amplifier for determining the positive or negative of the voltage change generated by the capacitors. This structure implements an A/D converter of high precision with less elements.

摘要翻译： A / D转换器包括产生参考电压的电阻网络，用于以来自电阻器网络的参考电压作为参考来检测输入模拟信号的电平的电平检测器，以及用于通过对输出进行编码来提供数字信号的编码器 的电平检测器。 电平检测器包括多个比较器，用于以来自电阻器网络的电阻器连接节点的预选电压作为参考电压对输入的模拟信号进行二维处理。 电阻网络包括在接收第一参考电压的第一节点和接收第二参考电压的第二节点之间的多个电阻器元件，其互连以提供来自相关联的连接节点的电压，所述相关联的连接节点是所述 第一参考电压和所述第二参考电压。 比较器包括用于通过电容器耦合提供输入模拟信号和参考电压之间的差异的电容器，以及用于确定由电容器产生的电压变化的正或负的反相放大器。 该结构实现了具有较低元件精度的A / D转换器。