公开(公告)号：US5818380A

公开(公告)日：1998-10-06

申请号：US824549

申请日：1997-03-25

申请人： Masao Ito ,  Takahiro Miki ,  Shiro Hosotani

发明人： Masao Ito ,  Takahiro Miki ,  Shiro Hosotani

IPC分类号： H03M1/10 ,  H03K19/23 ,  H03M1/06 ,  H03M1/36

CPC分类号： H03M1/0602 ,  H03M1/361

摘要： A majority logic circuit is supplied with output values of adjacent three comparators. The majority logic circuit outputs, as an output signal, the supplied three output values including at least two equal output values. Inverter circuits and AND circuits produce and output a read signal of an encoder which is a logical product between the output signal and an inverted signal of the output signal.

摘要翻译： 多数逻辑电路提供相邻三个比较器的输出值。 多数逻辑电路作为输出信号输出所提供的三个输出值，包括至少两个相等的输出值。 逆变器电路和AND电路产生并输出编码器的读取信号，该编码器是输出信号和输出信号的反相信号之间的逻辑积。

公开(公告)号：US5225837A

公开(公告)日：1993-07-06

申请号：US706834

申请日：1991-05-29

申请人： Shiro Hosotani ,  Takahiro Miki ,  Masao Ito

发明人： Shiro Hosotani ,  Takahiro Miki ,  Masao Ito

IPC分类号： H03M1/36 ,  H03M1/78

CPC分类号： H03M1/362

摘要： An A/D converter includes a resistor network generating a reference voltage, a level detector for detecting the level of an input analogue signal with a reference voltage from the resistor network as a reference, and an encoder for providing a digital signal by encoding the output of the level detector. The level detector includes a plurality of comparators for bilevel-processing the input analogue signal with a preselected voltage from the resistor connection nodes of the resistor network as a reference voltage. The resistor network comprises a plurality of resistor elements between a first node receiving a first reference voltage and a second node receiving a second reference voltage, which are interconnected to provide a voltage from an associated connection node that is 1/2.sup.j times the difference between said first reference voltage and said second reference voltage. The comparator includes capacitors for providing the difference between the input analogue signal and the reference voltage by a capacitor coupling, and an inverter amplifier for determining the positive or negative of the voltage change generated by the capacitors. This structure implements an A/D converter of high precision with less elements.

摘要翻译： A / D转换器包括产生参考电压的电阻网络，用于以来自电阻器网络的参考电压作为参考来检测输入模拟信号的电平的电平检测器，以及用于通过对输出进行编码来提供数字信号的编码器 的电平检测器。 电平检测器包括多个比较器，用于以来自电阻器网络的电阻器连接节点的预选电压作为参考电压对输入的模拟信号进行二维处理。 电阻网络包括在接收第一参考电压的第一节点和接收第二参考电压的第二节点之间的多个电阻器元件，其互连以提供来自相关联的连接节点的电压，所述相关联的连接节点是所述 第一参考电压和所述第二参考电压。 比较器包括用于通过电容器耦合提供输入模拟信号和参考电压之间的差异的电容器，以及用于确定由电容器产生的电压变化的正或负的反相放大器。 该结构实现了具有较低元件精度的A / D转换器。

公开(公告)号：US5315301A

公开(公告)日：1994-05-24

申请号：US976056

申请日：1992-11-13

申请人： Shiro Hosotani ,  Takahiro Miki ,  Masao Ito

发明人： Shiro Hosotani ,  Takahiro Miki ,  Masao Ito

IPC分类号： H03M1/08 ,  H03M1/06 ,  H03M1/36

CPC分类号： H03M1/0643 ,  H03M1/068 ,  H03M1/361

摘要： An improved parallel-type A/D converter is disclosed, which includes encoder 3 constituted by a pseudo-NMOS type ROM, and encoder 28 constituted by a pseudo-PMOS type ROM. These encoders are connected to the outputs of pre-encoder 2. Averaging circuit 29 receives binary data provided from two encoders to provide average value data of these as converted binary output data. Even in case of multi-addressing, an averaging circuit can provide correct data as converted data. As a result, an A/D converter which is not affected by noise or the like has been obtained.

摘要翻译： 公开了一种改进的并行型A / D转换器，其包括由伪NMOS型ROM构成的编码器3和由伪PMOS型ROM构成的编码器28。 这些编码器连接到预编码器2的输出。平均电路29接收从两个编码器提供的二进制数据，以将它们的平均值数据提供为转换的二进制输出数据。 即使在多寻址的情况下，平均电路也可以提供作为转换数据的正确数据。 结果，已经获得了不受噪声等影响的A / D转换器。

公开(公告)号：US5146112A

公开(公告)日：1992-09-08

申请号：US708019

申请日：1991-05-31

申请人： Masao Ito ,  Shiro Hosotani

发明人： Masao Ito ,  Shiro Hosotani

IPC分类号： G06G7/12 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/04 ,  H01L27/088 ,  H01L27/092 ,  H03K5/24 ,  H03K17/16

CPC分类号： H01L27/088 ,  H03K5/2481 ,  H03K5/249 ,  H01L27/0203

摘要： A semiconductor integrated circuit device having an analogue signal processing circuit and a digital signal processing circuit formed on a single semiconductor substrate is disclosed. As an example of the analogue signal processing circuit, a voltage comparator is described. Being liable to be affected by noise, an inverter 2 is formed of an NMOS transistor 41 and a resistance R. For transistor 41 is formed in a well region having a conductivity type (p) opposite to the conductivity type of the substrate (n), it is not easily influenced by noise transmitted through the substrate. Therefore, a voltage comparator independent of the adverse effect of noise from the digital signal processing circuit is obtained.

摘要翻译： 公开了一种具有模拟信号处理电路和形成在单个半导体衬底上的数字信号处理电路的半导体集成电路器件。 作为模拟信号处理电路的示例，描述了电压比较器。 容易受到噪声的影响，逆变器2由NMOS晶体管41和电阻R形成。晶体管41形成在具有与衬底（n）的导电类型相反的导电类型（p）的阱区中， ，不容易受到透过基板的噪声的影响。 因此，获得独立于来自数字信号处理电路的噪声的不利影响的电压比较器。

公开(公告)号：US5349354A

公开(公告)日：1994-09-20

申请号：US29426

申请日：1993-03-09

申请人： Masao Ito ,  Shiro Hosotani

发明人： Masao Ito ,  Shiro Hosotani

IPC分类号： H03M1/14 ,  H03M1/36

CPC分类号： H03M1/144 ,  H03M1/365

摘要： An improved serial-parallel type A/D converter is disclosed herein. A gate circuit 7 applies signals S11' to S14' provided from an encoder 3 only in a fine comparison period to switching circuits 11 to 14 as switching control signals S11 to S14. In the fine comparison period, one switching circuit is turned on, so that a fine comparison voltage is applied to voltage comparators 21 to 23. Since all of the switching circuits are turned off in a coarse comparison period, correct coarse comparison voltage is provided from a reference voltage generating circuit. As a result, a correct conversion in the coarse comparison period can be performed.

摘要翻译： 本文公开了一种改进的串并联型A / D转换器。 门电路7仅在精细比较期间将从编码器3提供的信号S11'应用于切换电路11至14作为切换控制信号S11至S14。 在精细的比较时段中，一个开关电路导通，使得精确的比较电压被施加到电压比较器21至23.由于所有的开关电路在粗略的比较周期中被关断，因此从 参考电压发生电路。 结果，可以进行粗略比较期间的正确转换。

公开(公告)号：US5140186A

公开(公告)日：1992-08-18

申请号：US631649

申请日：1990-12-21

申请人： Masao Ito ,  Shiro Hosotani

发明人： Masao Ito ,  Shiro Hosotani

IPC分类号： H03K5/08 ,  H03K5/24

CPC分类号： H03K5/249

摘要： A voltage comparator includes a coupling capacitor which receives at one terminal thereof two signals applied in a complementary fashion, an inverting amplifier having an input coupled to the other terminal of the coupling capacitor and having an output, and switch means coupled between the input and output of the inverting amplifier so as to be in parallel with the inverting amplifier. The duration of an auto-zeroing interval during which the switch means is conductive is maintained constant regardless of the period of the ON-OFF operation of the switch means.

摘要翻译： 电压比较器包括耦合电容器，其在一个端子处接收以互补方式施加的两个信号，反相放大器具有耦合到耦合电容器的另一端并具有输出的输入，以及耦合在输入和输出之间的开关装置 的反相放大器，以便与反相放大器并联。 开关装置导通的自动归零间隔的持续时间保持恒定，而与开关装置的ON-OFF操作的周期无关。

公开(公告)号：US5302869A

公开(公告)日：1994-04-12

申请号：US952421

申请日：1992-09-29

申请人： Shiro Hosotani ,  Masao Ito

发明人： Shiro Hosotani ,  Masao Ito

IPC分类号： H03K5/24 ,  H03M1/14 ,  H03M1/36

CPC分类号： H03K5/249 ,  H03M1/148 ,  H03M1/365

摘要： A voltage comparator for use in a subranging A/D converter includes a coarse preceding comparison circuit 30, a fine preceding comparison circuit 31, and an amplification circuit 32 having an automatic zero compensation function. The coarse preceding comparison circuit 30 compares an analog input voltage Vin and a coarse reference voltage Vai. The fine preceding comparison circuit 31 compares the analog input voltage Vin and a fine reference voltage Vbi. The coarse and fine preceding comparison circuits 30, 31 sequentially outputs comparison results to the amplification circuits 32 so that the comparison results do not overlap each other. The amplification circuits 32 resets offset voltages before amplifying the comparison results applied. The number of elements necessary for a subranging A/D converter can be reduced, and a voltage comparator operating at a high speed and highly accurately can be provided.

摘要翻译： 用于辅助A / D转换器的电压比较器包括粗略的先前比较电路30，精细的先前比较电路31和具有自动零点补偿功能的放大电路32。 粗略的比较电路30将模拟输入电压Vin和粗参考电压Vai进行比较。 精细的先前比较电路31将模拟输入电压Vin和精细参考电压Vbi进行比较。 粗略和精细的先前比较电路30,31顺序地将比较结果输出到放大电路32，使得比较结果彼此不重叠。 放大电路32在放大所施加的比较结果之前复位偏移电压。 可以减少子空间A / D转换器所需的元件的数量，并且可以提供高速且高精度地操作的电压比较器。

公开(公告)号：US06069579A

公开(公告)日：2000-05-30

申请号：US131238

申请日：1998-08-07

申请人： Masao Ito ,  Takeshi Shigenobu ,  Toshio Kumamoto ,  Takahiro Miki ,  Hiroshi Komurasaki

发明人： Masao Ito ,  Takeshi Shigenobu ,  Toshio Kumamoto ,  Takahiro Miki ,  Hiroshi Komurasaki

IPC分类号： H03M1/14 ,  H03M1/20 ,  H03M1/36 ,  H03M1/12

CPC分类号： H03M1/205 ,  H03M1/141

摘要： An A/D converter simplifies its circuit configuration without deteriorating accuracy in A/D conversion. A circuit is formed of a folding and interpolation type. A gain-variable pre-amplifier group 11 amplifies each of reference voltages Vref1 to VrefN and an analog input voltage Vin, to output the result to a folding amplifier group 12, while a gain-variable pre-amplifier group 21 amplifies each of reference voltages Vrr1 to VrrJ and the analog input voltage Vin, to output the result to a comparator group 24. Each of pre-amplifiers constituting the gain-variable pre-amplifier groups 11 and 21 has an amplification factor that varies in upper and lower comparison periods according to a clock control signal .PHI.cnt.

摘要翻译： A / D转换器简化了其电路配置，而不会降低A / D转换的精度。 电路由折叠和内插形式组成。 增益可变前置放大器组11放大每个参考电压Vref1至VrefN和模拟输入电压Vin，以将结果输出到折叠放大器组12，而增益可变的前置放大器组21放大每个参考电压 Vrr1至VrrJ和模拟输入电压Vin，将结果输出到比较器组24.构成增益可变前置放大器组11和21的每个前置放大器具有在上和下比较周期内变化的放大系数， 到时钟控制信号PHI cnt。

公开(公告)号：US5497120A

公开(公告)日：1996-03-05

申请号：US350030

申请日：1994-11-29

申请人： Masao Ito ,  Takahiro Miki

发明人： Masao Ito ,  Takahiro Miki

IPC分类号： G01R19/165 ,  H03F1/30 ,  H03F3/45 ,  H03K17/16

CPC分类号： G01R19/16519 ,  H03F1/303 ,  H03F3/45076

摘要： A differential amplifier circuit is obtained in which an operating power source voltage is suppressed to a minimum necessary level. The differential amplifier circuit includes a bias circuit having a differential amplifier with NMOS transistors (11A, 11B, 12A and 12B) and PMOS transistors (13A and 13B). Sources of NMOS transistors (11A)and (11B) are commonly grounded. A bias voltage (VB1) is supplied to gates of the NMOS transistors (11A) and (11B). Drains of the NMOS transistors (11A) and (11B) are connected to sources of NMOS transistors (12A) and (12B), respectively. A gate and a drain of the NMOS transistor (12A) are short-circuited to each other with the drain connected to a drain of a PMOS transistor (13A). A bias voltage (VB4) is applied to a gate of the NMOS transistor (12B). A drain of the NMOS transistor (12B) is connected to a drain of the PMOS transistor (13B) whose gate and drain are shared by each other. Gates of the PMOS transistors (13A) and (13B) are connected to a bias terminal (72) while sources of the PMOS transistors (13A) and (13B) are commonly connected to a power source. The bias terminal (72) is connected to an input bias terminal of a differential amplifier.

摘要翻译： 获得了将工作电源电压抑制到最小必要水平的差分放大电路。 差分放大器电路包括具有NMOS晶体管（11A，11B，12A和12B）和PMOS晶体管（13A和13B）的差分放大器的偏置电路。 NMOS晶体管（11A）和（11B）的源极通常接地。 偏置电压（VB1）被提供给NMOS晶体管（11A）和（11B）的栅极。 NMOS晶体管（11A）和（11B）的漏极分别连接到NMOS晶体管（12A）和（12B）的源极。 NMOS晶体管（12A）的栅极和漏极彼此短路，漏极连接到PMOS晶体管（13A）的漏极。 偏置电压（VB4）施加到NMOS晶体管（12B）的栅极。 NMOS晶体管（12B）的漏极连接到其栅极和漏极彼此共享的PMOS晶体管（13B）的漏极。 PMOS晶体管（13A）和（13B）的栅极连接到偏置端子（72），而PMOS晶体管（13A）和（13B）的源极共同连接到电源。 偏置端子（72）连接到差分放大器的输入偏置端子。

公开(公告)号：US5995031A

公开(公告)日：1999-11-30

申请号：US968207

申请日：1997-11-12

申请人： Takashi Okuda ,  Toshio Kumamoto ,  Masao Ito ,  Takahiro Miki

发明人： Takashi Okuda ,  Toshio Kumamoto ,  Masao Ito ,  Takahiro Miki

IPC分类号： H03M1/10 ,  H03M1/06 ,  H03M1/74 ,  H03M1/66

CPC分类号： H03M1/0663 ,  H03M1/747 ,  H03M3/464 ,  H03M3/502

摘要： A multi-bit D/A converter which improves the linearity of an analog output relative to a digital input is provided. A switch control circuit (1) turns on D some of a plurality of switches (S1 to SM) which are arranged in ascending order starting with a switch determined by a start position determination circuit (3) and turns off the remaining switches, the number of switches turned on being dependent on a digital signal (DIG). The start position determination circuit (3) sequentially changes the switches (S1, S3, S5, . . . ) serving as a selection start position to determine the selection start position for each input of the digital signal (DIG) provided in synchronism with a clock signal (CLK).

摘要翻译： 提供了一种提高模拟输出相对于数字输入的线性度的多位D / A转换器。 开关控制电路（1）接通D开始的开关位置确定电路（3）确定的开关的升序排列的多个开关（S1至SM）中的一些，并且关闭其余的开关 开关依赖于数字信号（DIG）。 开始位置确定电路（3）顺序地改变用作选择开始位置的开关（S1，S3，S5 ...），以确定与设置的与数字信号（DIG）同步的数字信号（DIG）的每个输入的选择开始位置 时钟信号（CLK）。