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    Scavenging metal stack for a high-K gate dielectric
    53.
    发明授权
    Scavenging metal stack for a high-K gate dielectric 有权
    用于高K栅极电介质的清除金属堆叠

    公开(公告)号：US08735996B2

    公开(公告)日：2014-05-27

    申请号：US13547772

    申请日：2012-07-12

    申请人： Takashi Ando ,  Unoh Kwon ,  Vijay Narayanan ,  James K. Schaeffer

    发明人： Takashi Ando ,  Unoh Kwon ,  Vijay Narayanan ,  James K. Schaeffer

    IPC分类号： H01L29/78 ,  H01L29/49 ,  H01L21/8238 ,  H01L29/51

    CPC分类号： H01L29/4958 ,  H01L21/28088 ,  H01L21/823828 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66507 ,  H01L29/6659 ,  H01L29/7833

    摘要： A semiconductor structure is provided. The structure includes a semiconductor substrate of a semiconductor material and a gate dielectric having a high dielectric constant dielectric layer with a dielectric constant greater than silicon. The gate dielectric is located on the semiconductor substrate. A gate electrode abuts the gate dielectric. The gate electrodes includes a lower metal layer abutting the gate dielectric, a scavenging metal layer abutting the lower metal layer, an upper metal layer abutting the scavenging metal layer, and a silicon layer abutting the upper metal layer. The scavenging metal layer reduces an oxidized layer at an interface between the upper metal layer and the silicon layer responsive to annealing.

    摘要翻译： 提供半导体结构。 该结构包括半导体材料的半导体衬底和具有介电常数大于硅的介电常数介电层的栅极电介质。 栅极电介质位于半导体衬底上。 栅电极邻接栅极电介质。 栅电极包括邻接栅电介质的下金属层，邻接下金属层的扫除金属层，与清扫金属层邻接的上金属层和邻接上金属层的硅层。 清除金属层响应于退火而在上金属层和硅层之间的界面处减少氧化层。

    REPLACEMENT METAL GATE WITH A CONDUCTIVE METAL OXYNITRIDE LAYER
    56.
    发明申请
    REPLACEMENT METAL GATE WITH A CONDUCTIVE METAL OXYNITRIDE LAYER 有权
    用导电金属氧化物层替代金属栅

    公开(公告)号：US20130009257A1

    公开(公告)日：2013-01-10

    申请号：US13177692

    申请日：2011-07-07

    申请人： Takashi Ando ,  Vijay Narayanan

    发明人： Takashi Ando ,  Vijay Narayanan

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L21/28088 ,  H01L21/28176 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/78654

    摘要： A disposable gate structure and a gate spacer are formed on a semiconductor substrate. A disposable gate material portion is removed and a high dielectric constant (high-k) gate dielectric layer and a metal nitride layer are formed in a gate cavity and over a planarization dielectric layer. The exposed surface portion of the metal nitride layer is converted into a metal oxynitride by a surface oxidation process that employs exposure to ozonated water or an oxidant-including solution. A conductive gate fill material is deposited in the gate cavity and planarized to provide a metal gate structure. Oxygen in the metal oxynitride diffuses, during a subsequent anneal process, into a high-k gate dielectric underneath to lower and stabilize the work function of the metal gate without significant change in the effective oxide thickness (EOT) of the high-k gate dielectric.

    摘要翻译： 在半导体衬底上形成一次性栅极结构和栅极间隔物。 去除一次性栅极材料部分，并且在栅极腔中和平坦化介电层上形成高介电常数（高k）栅极电介质层和金属氮化物层。 金属氮化物层的暴露表面部分通过使用暴露于臭氧化水或含氧化剂的溶液的表面氧化工艺转化为金属氮氧化物。 导电栅极填充材料沉积在栅极腔中并被平坦化以提供金属栅极结构。 金属氧氮化物中的氧在随后的退火过程中扩散到下面的高k栅极电介质中，以降低和稳定金属栅极的功函数，而不会在高k栅极电介质的有效氧化物厚度（EOT）上显着变化 。

    Gate-last fabrication of quarter-gap MGHK FET
    57.
    发明授权
    Gate-last fabrication of quarter-gap MGHK FET 失效
    最后制造四分之一MGHK FET

    公开(公告)号：US08786030B2

    公开(公告)日：2014-07-22

    申请号：US13570388

    申请日：2012-08-09

    申请人： Takashi Ando ,  Kisik Choi ,  Vijay Narayanan ,  Tenko Yamashita ,  Junli Wang

    发明人： Takashi Ando ,  Kisik Choi ,  Vijay Narayanan ,  Tenko Yamashita ,  Junli Wang

    IPC分类号： H01L21/02

    CPC分类号： H01L29/517 ,  H01L21/28079 ,  H01L21/28088 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545

    摘要： A quarter-gap p-type field effect transistor (PFET) formed by gate-last fabrication includes a gate stack formed on a silicon substrate, the gate stack including: a high-k dielectric layer located on the silicon substrate; and a gate metal layer located over the high-k dielectric layer, the gate metal layer including titanium nitride and having a thickness of about 20 angstroms; and a metal contact formed over the gate stack. A quarter-gap n-type field effect transistor (NFET) formed by gate-last fabrication includes a gate stack formed on a silicon substrate, the gate stack including: a high-k dielectric layer located on the silicon substrate; and a first gate metal layer located over the high-k dielectric layer, the first gate metal layer including titanium nitride; and a metal contact formed over the gate stack.

    摘要翻译： 通过栅极最终制造形成的四分之一间隙p型场效应晶体管（PFET）包括形成在硅衬底上的栅极堆叠，所述栅极堆叠包括：位于硅衬底上的高k电介质层; 以及位于高k电介质层上方的栅极金属层，所述栅极金属层包括氮化钛并且具有约20埃的厚度; 以及形成在栅极堆叠上的金属接触。 通过栅极最后制造形成的四分之一间隙n型场效应晶体管（NFET）包括形成在硅衬底上的栅极堆叠，该栅极堆叠包括：位于硅衬底上的高k电介质层; 以及位于所述高k电介质层上方的第一栅极金属层，所述第一栅极金属层包括氮化钛; 以及形成在栅极堆叠上的金属接触。

    Replacement gate devices with barrier metal for simultaneous processing
    58.
    发明授权
    Replacement gate devices with barrier metal for simultaneous processing 失效
    具有隔离金属的替换门装置用于同时处理

    公开(公告)号：US08420473B2

    公开(公告)日：2013-04-16

    申请号：US12960586

    申请日：2010-12-06

    申请人： Takashi Ando ,  Michael P. Chudzik ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Vijay Narayanan

    发明人： Takashi Ando ,  Michael P. Chudzik ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Vijay Narayanan

    IPC分类号： H01L21/8238 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC分类号： H01L21/823842 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/7848

    摘要： A method of simultaneously fabricating n-type and p type field effect transistors can include forming a first replacement gate having a first gate metal layer adjacent a gate dielectric layer in a first opening in a dielectric region overlying a first active semiconductor region. A second replacement gate including a second gate metal layer can be formed adjacent a gate dielectric layer in a second opening in a dielectric region overlying a second active semiconductor region. At least portions of the first and second gate metal layers can be stacked in a direction of their thicknesses and separated from each other by at least a barrier metal layer. The NFET resulting from the method can include the first active semiconductor region, the source/drain regions therein and the first replacement gate, and the PFET resulting from the method can include the second active semiconductor region, source/drain regions therein and the second replacement gate.

    摘要翻译： 同时制造n型和p型场效应晶体管的方法可以包括在覆盖第一有源半导体区域的电介质区域中的第一开口中形成具有与栅极电介质层相邻的第一栅极金属层的第一替代栅极。 包括第二栅极金属层的第二替代栅极可以在覆盖在第二有源半导体区域上的电介质区域中的第二开口中邻近栅极电介质层形成。 第一和第二栅极金属层的至少一部分可以沿其厚度的方向堆叠并且通过至少阻挡金属层彼此分离。 由该方法产生的NFET可以包括第一有源半导体区域，其中的源极/漏极区域和第一替换栅极，并且由该方法产生的PFET可以包括第二有源半导体区域，其中的源/漏区域和第二替换 门。

    Gate-Last Fabrication of Quarter-Gap MGHK FET
    59.
    发明申请
    Gate-Last Fabrication of Quarter-Gap MGHK FET 失效
    最近制造四分之一间隙MGHK FET

    公开(公告)号：US20120299123A1

    公开(公告)日：2012-11-29

    申请号：US13570388

    申请日：2012-08-09

    申请人： Takashi Ando ,  Kisik Choi ,  Vijay Narayanan ,  Tenko Yamashita ,  Junli Wang

    发明人： Takashi Ando ,  Kisik Choi ,  Vijay Narayanan ,  Tenko Yamashita ,  Junli Wang

    IPC分类号： H01L29/78

    CPC分类号： H01L29/517 ,  H01L21/28079 ,  H01L21/28088 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545

    摘要： A quarter-gap p-type field effect transistor (PFET) formed by gate-last fabrication includes a gate stack formed on a silicon substrate, the gate stack including: a high-k dielectric layer located on the silicon substrate; and a gate metal layer located over the high-k dielectric layer, the gate metal layer including titanium nitride and having a thickness of about 20 angstroms; and a metal contact formed over the gate stack. A quarter-gap n-type field effect transistor (NFET) formed by gate-last fabrication includes a gate stack formed on a silicon substrate, the gate stack including: a high-k dielectric layer located on the silicon substrate; and a first gate metal layer located over the high-k dielectric layer, the first gate metal layer including titanium nitride; and a metal contact formed over the gate stack.

    摘要翻译： 通过栅极最终制造形成的四分之一间隙p型场效应晶体管（PFET）包括形成在硅衬底上的栅极堆叠，所述栅极堆叠包括：位于硅衬底上的高k电介质层; 以及位于高k电介质层上方的栅极金属层，所述栅极金属层包括氮化钛并且具有约20埃的厚度; 以及形成在栅极堆叠上的金属接触。 通过栅极最后制造形成的四分之一间隙n型场效应晶体管（NFET）包括形成在硅衬底上的栅极堆叠，该栅极堆叠包括：位于硅衬底上的高k电介质层; 以及位于所述高k电介质层上方的第一栅极金属层，所述第一栅极金属层包括氮化钛; 以及形成在栅极堆叠上的金属接触。