公开(公告)号：US07474584B2

公开(公告)日：2009-01-06

申请号：US11833190

申请日：2007-08-02

申请人： Masanao Yamaoka ,  Koichiro Ishibashi ,  Shigezumi Matsui ,  Kenichi Osada

发明人： Masanao Yamaoka ,  Koichiro Ishibashi ,  Shigezumi Matsui ,  Kenichi Osada

IPC分类号： G11C5/14

CPC分类号： G11C11/419 ,  G11C5/146 ,  G11C5/147 ,  G11C11/4125 ,  G11C11/417 ,  G11C2207/2227

摘要： A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.

摘要翻译： 系统LSI中的逻辑电路设置有电源开关，以便在待机时切断开关，从而减少漏电流。 同时，系统LSI的SRAM电路控制衬底偏置以减少漏电流。

公开(公告)号：US20080203437A1

公开(公告)日：2008-08-28

申请号：US12078992

申请日：2008-04-09

申请人： Kenichi Osada ,  Koichiro Ishibashi ,  Yoshikazu Saitoh ,  Akio Nishida ,  Masaru Nakamichi ,  Naoki Kitai

发明人： Kenichi Osada ,  Koichiro Ishibashi ,  Yoshikazu Saitoh ,  Akio Nishida ,  Masaru Nakamichi ,  Naoki Kitai

IPC分类号： H01L27/11 ,  G11C11/40

CPC分类号： G11C11/412 ,  G11C11/40 ,  G11C11/413 ,  G11C11/418 ,  H01L21/823475 ,  H01L21/823493 ,  H01L21/823814 ,  H01L21/82385 ,  H01L27/088 ,  H01L27/092 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H03K19/0016

摘要： The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.

摘要翻译： 在最新的工艺中，栅极隧道泄漏电流增加，因此需要减小由用于蜂窝电话的电池驱动的LSI中的栅极隧道泄漏电流，并且需要在 待机模式处于低漏电流。 在半导体集成电路器件中，逻辑和存储电路的接地源电极线保持在有源模式的接地电位，并且在未选择待机模式下保持在比地电位高的电压。 可以减少栅极漏电流而不破坏数据。

公开(公告)号：US07397693B2

公开(公告)日：2008-07-08

申请号：US11657026

申请日：2007-01-24

申请人： Masanao Yamaoka ,  Kenichi Osada ,  Koichiro Ishibashi

发明人： Masanao Yamaoka ,  Kenichi Osada ,  Koichiro Ishibashi

IPC分类号： G11C11/00

CPC分类号： G11C11/417 ,  G11C11/412 ,  Y10S257/903

摘要： A memory using an SRAM memory cell intended for low-voltage operation is designed to decrease the threshold value of MOS transistors constituting the memory cell without substantial decrease in the static noise margin, which is the operational margin of the memory cell. To this end, a voltage Vdd′ higher than a power supply voltage Vdd of a power supply line for peripheral circuits is supplied from a power supply line for memory cells as a power supply voltage for memory cells. Since the conductance of driver MOS transistors is in-creased, the threshold voltage of the MOS transistors within the memory cells can be reduced without reducing the static noise margin. Further the ratio of width between the driver MOS transistor and a transfer MOS transistor can be set to 1, thereby allowing a reduction in the memory cell area.

摘要翻译： 使用用于低电压操作的SRAM存储单元的存储器被设计为降低构成存储器单元的MOS晶体管的阈值，而不会显着降低静态噪声容限，这是存储单元的操作余量。 为此，作为存储单元的电源电压，从用于存储单元的电源线提供高于外围电路用电源线的电源电压Vdd的电压Vdd'。 由于驱动器MOS晶体管的电导被增加，所以可以在不降低静态噪声容限的情况下减小存储单元内的MOS晶体管的阈值电压。 此外，可以将驱动器MOS晶体管和转移MOS晶体管之间的宽度比设置为1，从而允许存储单元区域的减小。

公开(公告)号：US20080143423A1

公开(公告)日：2008-06-19

申请号：US11943095

申请日：2007-11-20

申请人： Shigenobu Komatsu ,  Kenichi Osada ,  Masanao Yamaoka ,  Koichiro Ishibashi

发明人： Shigenobu Komatsu ,  Kenichi Osada ,  Masanao Yamaoka ,  Koichiro Ishibashi

IPC分类号： H03K3/01 ,  H01L21/8238

CPC分类号： H01L27/092 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/1203 ,  H03K19/0027 ,  H03K19/00315

摘要： The present invention is directed to realize high manufacture yield and compensate variations in threshold voltage of a MOS transistor with small overhead. A semiconductor integrated circuit includes a CMOS circuit for processing an input signal in an active mode, a control switch, and a control memory. The control switch supplies a pMOS body bias voltage and an nMOS body bias voltage to an N well in a pMOS transistor and a P well in an nMOS transistor, respectively, in the CMOS circuit. The control memory stores control information indicating whether or not the pMOS body bias voltage and the nMOS body bias voltage are supplied from the control switch to the N well in the pMOS transistor and the P well in the nMOS transistor, respectively, in the CMOS circuit in the active mode.

摘要翻译： 本发明旨在实现高制造成品率并补偿具有较小开销的MOS晶体管的阈值电压的变化。 半导体集成电路包括用于处理活动模式中的输入信号的CMOS电路，控制开关和控制存储器。 控制开关分别向CMOS电路中的nMOS晶体管中的pMOS晶体管和P阱中的N阱施加pMOS体偏置电压和nMOS体偏置电压。 控制存储器存储指示pMOS体偏置电压和nMOS体偏置电压是否从控制开关提供到CMOS电路中的nMOS晶体管中的pMOS晶体管和P阱中的N阱的控制信息 处于活动模式。

公开(公告)号：US20080143184A1

公开(公告)日：2008-06-19

申请号：US11956122

申请日：2007-12-13

申请人： Kazuo OTSUGA ,  Tetsuya Yamada ,  Kenichi Osada ,  Yusuke Kanno

发明人： Kazuo OTSUGA ,  Tetsuya Yamada ,  Kenichi Osada ,  Yusuke Kanno

IPC分类号： H02J1/00 ,  G01R19/00

CPC分类号： G01R19/0092 ,  Y10T307/406

摘要： A semiconductor integrated circuit is constituted to include a circuit block having a predetermined function, a power switch capable of supplying an operating power to the circuit block, and a current measuring circuit for obtaining a current flowing to the circuit block based on a voltage between terminals of the power switch in a state in which the power switch is turned on and an on-resistance of the power switch. The current flowing to the circuit block is obtained based on the voltage between terminals of the power switch in the state in which the power switch is turned on and the on-resistance of the power switch. Thus, it is possible to measure a current of the circuit block in a state in which a chip is normally operated.

摘要翻译： 半导体集成电路被构成为包括具有预定功能的电路块，能够向电路块提供工作电力的电源开关，以及电流测量电路，用于根据端子之间的电压获得流向电路块的电流 电源开关处于电源开关接通的状态和电源开关的导通电阻。 基于电源开关接通状态和电源开关的导通电阻之间的电源开关电压之间的电流可以获得流向电路块的电流。 因此，可以在芯片正常工作的状态下测量电路块的电流。

公开(公告)号：US20080114967A1

公开(公告)日：2008-05-15

申请号：US11935790

申请日：2007-11-06

申请人： Makoto Saen ,  Kenichi Osada ,  Tetsuya Yamada ,  Yusuke Kanno ,  Satoshi Misaka

发明人： Makoto Saen ,  Kenichi Osada ,  Tetsuya Yamada ,  Yusuke Kanno ,  Satoshi Misaka

IPC分类号： G06F9/302

CPC分类号： G06F1/3228 ,  H01L2924/0002 ,  H01L2924/00

摘要： There is provided a semiconductor integrated circuit device which consumes less power and enables real-time processing. The semiconductor integrated circuit device comprises: thermal sensors which can detect temperature, determine whether the detection result exceeds each of the above reference values and output the result; and a control block capable of controlling the operations of arithmetic blocks based on the output signals of the thermal sensors, wherein the control block returns to an operation state from a suspended state with an interrupt signal based on the output signals of the thermal sensors and determines the operation conditions of the arithmetic blocks to ensure that the temperature conditions of the arithmetic blocks are satisfied. Thereby, power consumption is reduced and real-time processing efficiency is improved.

摘要翻译： 提供了一种半导体集成电路器件，其消耗较少功率并实现实时处理。 半导体集成电路装置包括：可以检测温度的热传感器，确定检测结果是否超过上述参考值，并输出结果; 以及控制块，其能够基于所述热传感器的输出信号来控制运算块的运算，其中，所述控制块基于所述热传感器的输出信号，利用中断信号从暂停状态返回到运行状态，并且确定 运算块的操作条件，以确保运算块的温度条件得到满足。 从而降低了功耗，提高了实时处理效率。

公开(公告)号：US07336526B2

公开(公告)日：2008-02-26

申请号：US11324357

申请日：2006-01-04

申请人： Kenichi Osada ,  Takayuki Kawahara

发明人： Kenichi Osada ,  Takayuki Kawahara

IPC分类号： G11C11/00

CPC分类号： G11C13/0004 ,  G11C5/147 ,  G11C8/08 ,  G11C13/0028 ,  G11C2213/79

摘要： To improve the reliability of the phase change element, unwanted current should not be flown into the element. Therefore, an object of the present invention is to provide a memory cell that stores information depending on a change in its state caused by applied heat, as well as an input/output circuit, and to turn off the word line until the power supply circuit is activated. According to the present invention, unwanted current flow to the element can be prevented and thereby data destruction can be prevented.

公开(公告)号：US20070263433A1

公开(公告)日：2007-11-15

申请号：US11812641

申请日：2007-06-20

申请人： Kenichi Osada ,  Kiyoo Itoh

发明人： Kenichi Osada ,  Kiyoo Itoh

IPC分类号： G11C5/06 ,  G11C11/00 ,  G11C8/00

CPC分类号： H01L27/24 ,  G11C7/04 ,  G11C13/0004

摘要： Memory blocks having memory cells which are comprised of vertical transistors and memory elements in which the resistance value is varied depending on the temperature imposed on the upper side thereof, are laminated to realize a highly-integrated non-volatile memory.

公开(公告)号：US20070246767A1

公开(公告)日：2007-10-25

申请号：US11812694

申请日：2007-06-21

申请人： Kenichi Osada ,  Takayuki Kawahara ,  Masanao Yamaoka

发明人： Kenichi Osada ,  Takayuki Kawahara ,  Masanao Yamaoka

IPC分类号： H01L29/76

CPC分类号： H01L29/78648 ,  G11C11/412 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/0928 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1203 ,  H01L29/4908 ,  H01L29/78609 ,  H01L2924/0002 ,  H01L2924/00

摘要： Thresholds of MISFETS of a Full Depletion-type SOI substrate cannot be controlled by changing impurity density as with bulk silicon MISFETs. Therefore, it is difficult to set a suitable threshold for each circuit. According to the semiconductor device of the present invention, gate electrodes of P-channel type MISFETs composing a memory cell are made of N-type polysilicon, gate electrodes of N-channel type MISFETs are made of P-type polysilicon and gate electrodes of P-channel type and N-channel type MISFETs of peripheral circuits and a logic circuit are made of P-type silicon germanium. A suitable threshold can be achieved for each circuit using a SOI substrate, thereby making it possible to fully leverage the characteristics of the SOI substrate.

摘要翻译： 完全耗尽型SOI衬底的MISFETS的阈值不能通过改变杂质密度来控制，就像体硅硅MISFET那样。 因此，难以为每个电路设定合适的阈值。 根据本发明的半导体器件，构成存储单元的P沟道型MISFET的栅电极由N型多晶硅制成，N沟道型MISFET的栅电极由P型多晶硅制成，栅电极为P 通道型和外围电路的N沟道型MISFET和逻辑电路由P型硅锗制成。 对于使用SOI衬底的每个电路，可以实现合适的阈值，从而可以充分利用SOI衬底的特性。

公开(公告)号：US07251157B2

公开(公告)日：2007-07-31

申请号：US10933336

申请日：2004-09-03

申请人： Kenichi Osada ,  Kiyoo Itoh

发明人： Kenichi Osada ,  Kiyoo Itoh

IPC分类号： G11C11/00

CPC分类号： H01L27/24 ,  G11C7/04 ,  G11C13/0004

摘要： Memory blocks having memory cells which are comprised of vertical transistors and memory elements in which the resistance value is varied depending on the temperature imposed on the upper side thereof, are laminated to realize a highly-integrated non-volatile memory.

摘要翻译： 具有由垂直晶体管构成的存储单元和其中电阻值根据其上侧施加的温度而变化的存储单元的存储器块被层叠以实现高度集成的非易失性存储器。